Burn-In Test Method for High Voltage MOS Transistors

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Solution Overview

Problem

The premature failure rate of integrated circuits due to gate oxide breakdown in high voltage transistors is a challenge, especially as memory miniaturization increases, and existing burn-in tests struggle to effectively identify and discard faulty circuits without increasing test durations.

Innovation Solution

A method that subjects high voltage MOS transistors in the conductive state to a first test voltage higher than normal operating voltage and those in the blocked state to a second test voltage lower than the first, while maintaining the voltage below the breakdown threshold, with the states of the transistors being changed between the two steps, to increase the effectiveness of burn-in tests without extending test durations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single high test voltage is applied to all high voltage transistors during burn-in test, then transistors in conductive state are effectively tested, but transistors in blocked state are insufficiently stressed and may escape detection

Engineering Contradiction:
Improvedetection effectivenessVSAvoidcoverage of all transistor states
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies dynamics by switching transistors between conductive and blocked states during the burn-in test. The method alternates the operational state of high voltage transistors to ensure both states are subjected to appropriate stress voltages, making the test adaptive rather than static.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies local quality by applying different test voltages tailored to specific transistor states. Transistors in conductive state receive a first test voltage, while transistors in blocked state receive a second test voltage, ensuring each state receives the appropriate stress level for effective detection.

Inventive Principle:
Principle #3Local quality

2Measurement precision

If test voltage is increased to detect weaker transistors, then detection precision improves, but risk of exceeding breakdown voltage and causing false failures increases

Engineering Contradiction:
Improvedetection precisionVSAvoidbreakdown risk
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the test voltage level based on the transistor's operational state. The method uses two distinct voltage levels: a first test voltage for conductive state and a second test voltage for blocked state, both optimized to maximize detection precision while remaining below the breakdown threshold.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies beforehand cushioning by carefully selecting test voltages that are high enough to stress weak transistors but deliberately kept below the breakdown voltage. This preventive approach ensures that the test stresses components sufficiently to detect defects without causing catastrophic failure that would mask the detection capability.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If burn-in test duration is extended to improve detection, then reliability improves, but productivity decreases

Engineering Contradiction:
Improvedetection effectivenessVSAvoidtest throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies periodic action by alternating between different test phases that stress transistors in different states. The method periodically switches transistors between conductive and blocked states during the burn-in test, enabling comprehensive coverage of all transistor states within a standardized test duration without extension.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS9001602B2Method of burn-in test of EEPROM or flash memories
Publication Date: 2015.04.07 STMICROELECTRONICS (ROUSSET) SAS
  • US9001602B2 patent drawing
  • US9001602B2 patent drawing
  • US9001602B2 patent drawing

AI summary

A method for testing an integrated circuit includes, in a burn-in test mode, two steps during which gate oxides of conductive high voltage MOS transistors of the integrated circuit are subjected to a first test voltage, and blocked high voltage MOS transistors of the integrated circuit are subjected to a second test voltage. The first test voltage is set to a value higher than a high supply voltage supplied to the high voltage MOS transistors in a normal operating mode, to make the gate oxides of transistors considered as insufficiently robust break down. The second test voltage is set to a value lower than the first test voltage and which can be supported by the blocked transistors, the states of the transistors being changed between the two steps.