Semiconductor Burn-In Test Omission via Probe Data Segmentation
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Solution Overview
Problem
The semiconductor device manufacturing process is costly due to the lengthy and mandatory burn-in test process, which accounts for a significant portion of the total test cost, and existing techniques cannot eliminate the necessity of performing a burn-in test.
Innovation Solution
Determining whether each semiconductor chip requires a burn-in test based on measurement data from the probe test process, sorting packages into lots that require or do not require a burn-in test, and omitting the burn-in test for those that do not, using a determination model generated through data learning and statistical analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a burn-in test is performed on all semiconductor chips, then reliability is improved, but productivity deteriorates due to the long test time
Solution Approach 1:
The patent segments the semiconductor chip population into two distinct groups: high-risk chips that require burn-in testing and low-risk chips that can skip burn-in. This segmentation is achieved by analyzing probe test measurement data to identify chips with specific characteristics indicating higher failure risk, thereby applying burn-in testing only where necessary rather than universally to all chips.
Solution Approach 2:
The patent applies local quality by treating different chips differently based on their individual risk profiles. Instead of applying a uniform burn-in test policy to all chips, the system evaluates each chip's probe test data and applies burn-in testing selectively to chips that exhibit characteristics of high failure risk, while allowing chips with low risk profiles to proceed without burn-in testing.
2Reliability
If a burn-in test is performed on all semiconductor chips, then reliability is improved, but cost increases due to the high test cost
Solution Approach 1:
The patent segments the chip population based on risk assessment from probe test data, dividing chips into high-risk and low-risk categories. This segmentation enables cost reduction by eliminating unnecessary burn-in testing for low-risk chips while maintaining reliability through continued burn-in testing of high-risk chips, thereby optimizing the overall cost structure.
Solution Approach 2:
The patent implements local quality by applying different test protocols to different chips based on their individual characteristics. Chips identified as low-risk through probe test analysis receive no burn-in testing, reducing cost, while chips identified as high-risk undergo burn-in testing to ensure reliability, achieving an optimized balance between cost and quality.
3Productivity
If the burn-in test time is reduced, then productivity is improved, but reliability deteriorates due to insufficient testing
Solution Approach 1:
The patent performs preliminary action by conducting probe testing and analyzing measurement data before the burn-in test stage. This preliminary risk assessment identifies which chips are likely to fail, enabling the system to determine in advance which chips require burn-in testing and which can skip it, thereby optimizing both productivity and reliability decisions before committing to the time-consuming burn-in process.
Solution Approach 2:
The patent utilizes feedback from probe test measurement data to inform burn-in test decisions. By analyzing characteristics from the probe test stage and using this feedback to identify high-risk chips, the system can selectively apply burn-in testing only where the feedback indicates potential failure risks, thereby maintaining reliability while improving productivity by avoiding unnecessary testing of low-risk chips.
Data Source
AI summary
A semiconductor device manufacturing method includes forming a plurality of semiconductor chips on a main surface of a semiconductor wafer, electrically testing each of the semiconductor chips, dicing the semiconductor wafer into individual semiconductor chips and assembling each of the semiconductor chips into a package to be a semiconductor device, subjecting the packages to a burn-in test, determining whether each of the semiconductor chips requires the burn-in test to be performed, and generating a determination model for determining whether the semiconductor chips require the burn-in test to be performed.