Burn-in Testing for III-N Semiconductor Devices
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Solution Overview
Problem
The reliability of high-power III-N semiconductor devices is challenging due to manufacturing defects and latent defects that are not detected by conventional probe testing, leading to early-life failures or 'infant mortality' in power electronic applications, which requires a more robust screening procedure.
Innovation Solution
A burn-in testing method involving multiple temperature and voltage steps is employed to screen III-N devices, including a low-temperature and high-temperature burn-in process, where devices are subjected to specific gate-source and drain-source voltage conditions to accelerate the detection of latent defects, thereby reducing the time required for burn-in testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional probe testing is used to screen III-N devices, then the testing process is simple and fast, but latent defects are not detected leading to early-life failures
Solution Approach 1:
The burn-in testing process applies preliminary stress conditions (elevated temperature and voltage) to III-N devices before they are deployed in commercial applications. This preliminary action accelerates the manifestation of latent defects, allowing defective devices to be identified and removed from the population prior to deployment, thereby improving overall device reliability without requiring complex in-service monitoring systems
Solution Approach 2:
The invention changes the testing parameters by applying elevated temperature (e.g., 150°C to 200°C) and voltage stress conditions that exceed normal operating parameters. These parameter changes accelerate defect manifestation and device failure mechanisms, enabling latent defects to be detected during the burn-in process rather than during actual product operation, thus resolving the contradiction between reliability improvement and testing complexity
2Reliability
If burn-in testing is performed at high temperature and voltage to detect latent defects, then device reliability is improved, but the burn-in time increases
Solution Approach 1:
The invention optimizes the burn-in parameters by applying specific temperature ranges (150°C to 200°C) and voltage stress levels that are sufficiently high to accelerate defect manifestation but controlled to avoid excessive device degradation. This parameter optimization enables latent defects to be detected within a reduced time frame compared to conventional lower-stress burn-in methods, thereby improving reliability while minimizing time loss
Solution Approach 2:
The burn-in process applies accelerated stress conditions that rush through the defect manifestation process by forcing latent defects to surface quickly under extreme temperature and voltage. This allows the testing to complete in a shorter time than would be required under normal operating conditions, effectively skipping the long period during which defective devices would otherwise operate undetected
3Measurement precision
If multiple temperature and voltage steps are applied in burn-in testing, then detection of latent defects is improved, but the testing procedure becomes more complex
Solution Approach 1:
The burn-in testing procedure is segmented into distinct temperature and voltage steps, each targeting specific defect mechanisms. For example, the process includes initial stress application, intermediate temperature adjustments, and final characterization phases. This segmentation allows each step to be optimized for detecting particular types of latent defects while maintaining clear procedural boundaries, improving defect detection accuracy without creating an unmanageably complex overall procedure
Solution Approach 2:
The invention systematically changes temperature and voltage parameters through defined steps and holds at each condition for specified durations. These controlled parameter changes enable the detection of different types of latent defects that manifest under specific stress conditions, improving measurement precision while maintaining a structured and manageable testing procedure through systematic parameter variation
Data Source
AI summary
Techniques for improving reliability of III-N devices include holding the III-N devices at a first temperature less than or equal to 30° for a first period of time while applying a first gate-source voltage lower than a threshold voltage of the III-N devices and a first drain-source voltage greater than 0.2 times a break down voltage of the III-N devices; and holding the III-N devices at a second temperature greater than the first temperature for a second period of time while applying a second gate-source voltage lower than a threshold voltage of the III-N devices and a second drain-source voltage greater than 0.2 times a breakdown voltage of the III-N devices. After holding the III-N devices at the first and second temperatures, screening the III-N devices based on electrical performance of one or more parameters of the III-N devices.