Burn-in Voltage Supply Lines for Semiconductor Memory Defect Detection
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Solution Overview
Problem
Conventional burn-in tests for semiconductor memory devices with open bit-line structures struggle to detect physical defects between memory cells due to the application of identical voltages to adjacent bit lines, limiting the effectiveness of defect detection during extreme conditions.
Innovation Solution
A semiconductor memory device and method that apply different burn-in voltages to adjacent bit lines through alternately coupled burn-in voltage supply lines, enabling the detection of physical defects by alternately activating word lines and using pre-charge and equalizer circuits to manage these voltages during the burn-in test.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If identical voltages are applied to adjacent bit lines during burn-in test, then the burn-in test can be performed with simple voltage supply, but physical defects between memory cells cannot be detected
Solution Approach 1:
The voltage supply structure is segmented into multiple independent burn-in voltage supply lines (first burn-in voltage supply line and second burn-in voltage supply line) that can provide different voltages to different bit lines. This segmentation enables differential voltage application to adjacent bit lines, allowing detection of physical defects between memory cells while maintaining manageable system complexity through modular voltage supply architecture.
Solution Approach 2:
Different burn-in voltages are applied locally to different bit lines based on their coupling to sense amplifier blocks. The first burn-in voltage is applied to odd-numbered sense amplifier blocks and the second burn-in voltage to even-numbered blocks, creating local voltage differentiation that enables defect detection at specific locations without requiring complex global voltage control.
2Productivity
If all word lines are activated simultaneously during burn-in test, then testing speed is improved, but voltage control precision deteriorates
Solution Approach 1:
Word lines are activated in periodic alternating patterns rather than simultaneously. Odd-numbered word lines are activated at one time period while even-numbered word lines are activated at another time period. This periodic activation allows the voltage supply system to maintain precise voltage control for each group while still achieving high testing speed through continuous alternating operation.
Data Source
AI summary
A semiconductor memory device includes a row decoder, a control circuit, and a memory cell array having an open bit-line structure. The memory cell array includes a plurality of word lines coupled to the row decoder, a plurality of bit lines, a plurality of memory cells, a plurality of sense amplifier blocks, and a plurality of burn-in voltage supply lines coupled to the plurality of sense amplifier blocks in a predetermined order, respectively. The control circuit controls the row decoder and the memory cell array for performing a burn-in test. During the burn-in test, the burn-in voltage supply lines are provided with at least two different burn-in voltages. The burn-in voltage supply lines respectively coupled to the sense amplifier blocks that are adjacent to each other are provided with different burn-in voltages during the burn-in test.