Burst Address Generator for Memory Testing
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Solution Overview
Problem
Existing memory device testing apparatuses lack the capability to generate diverse burst addresses efficiently, limiting their ability to thoroughly test data writing and reading functions in memory components.
Innovation Solution
A burst address generator is developed, comprising a burst bit counter, splitter, and selectors, which increase or decrease burst bits to generate X and Y burst addresses in synchronization with a reference clock, enabling the creation of various burst address patterns for comprehensive testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing memory device testing apparatuses are used, then the testing function is provided, but the capability to generate diverse burst addresses efficiently is lacking
Solution Approach 1:
The burst address generation is segmented into multiple independent components: a burst bit counter that generates sequential burst bits, a burst bit splitter that divides burst bits into X and Y burst bits, and selectors that combine base addresses with burst bits. This segmentation allows each component to operate independently and efficiently, enabling diverse burst address generation patterns while maintaining high productivity through parallel operation of the counter and splitter units.
2Adaptability or versatility
If a burst address generator with multiple components is implemented, then diverse burst address patterns can be generated, but the device complexity increases
Solution Approach 1:
The burst address generator employs universal components that can handle multiple functions: the burst bit counter generates sequential patterns for different burst lengths, the splitter can divide burst bits according to various X/Y address configurations, and the selectors can combine addresses with burst bits in different patterns. This multi-functionality allows the system to generate various burst address patterns without requiring separate dedicated circuits for each pattern type, thereby managing complexity while maintaining versatility.
Data Source
AI summary
A burst address generator includes a burst bit counter for receiving at least one burst bit, and increasing or decreasing the at least one burst bit, a burst bit splitter for receiving the increased or decreased at least one burst bit from the burst bit counter, and dividing the increased or decreased at least one burst bit into an X burst bit and a Y burst bit, and a selector for receiving an X address, a Y address, the X burst bit, and the Y burst bit, and generating an X burst address based on the X address and the X burst bit and a Y burst address based on the Y address and the Y burst bit.