Burst Mode CDR Circuit with Injection Locking for Fast Wideband Lock
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Solution Overview
Problem
Existing CDR circuits in PONs face challenges in achieving fast lock times over a wide range of frequencies, which is essential for maintaining errorless operation in burst data transmission.
Innovation Solution
A CDR circuit employing a frequency tracking loop with an injection locked oscillator and a phase tracking circuit comprising a phase interpolator and a finite state machine, which enables fast frequency and phase locking within less than 40 UIs across a wide range of frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional CDR architectures are used, then frequency tracking is achieved, but lock time is too long (hundreds to thousands of UI)
Solution Approach 1:
The CDR circuit is divided into two independent tracking loops: a frequency tracking loop using an injection-locked oscillator to quickly acquire frequency lock, and a phase tracking loop using a phase interpolator and finite state machine to achieve phase alignment. This segmentation allows each loop to be optimized for its specific function, with the frequency loop providing fast initial acquisition and the phase loop providing precise final alignment, thereby reducing overall lock time while ensuring reliable errorless operation.
2Loss of time
If burst mode CDRs with GVCOs are used, then fast locking is achieved, but control range is limited
Solution Approach 1:
The injection-locked oscillator is designed to accept a wide range of input frequencies and generate corresponding output frequencies, providing universal frequency coverage. The phase interpolator further extends this universality by enabling continuous phase adjustment across the entire frequency range. This multi-functional design allows the CDR circuit to maintain fast locking capability while adapting to various data rates and frequency requirements, significantly expanding the control range compared to traditional GVCO-based burst mode CDRs.
3Adaptability or versatility
If PI based CDRs are used, then wide frequency range is supported, but phase lock time is long (hundreds of UI)
Solution Approach 1:
The frequency tracking loop using the injection-locked oscillator performs preliminary frequency acquisition and stabilization before the phase tracking loop begins its operation. By pre-establishing frequency lock and providing a stable frequency reference to the phase interpolator, the preliminary action of the frequency loop significantly reduces the time required for the phase loop to achieve lock, thereby reducing overall phase lock time while maintaining wide frequency range support.
4Reliability
If state machines are used for phase tracking, then phase lock is achieved, but locking speed is slow
Solution Approach 1:
The finite state machine implements a feedback-based phase tracking mechanism that continuously monitors the phase difference between the recovered clock and the input data, and dynamically adjusts the phase interpolator accordingly. The feedback loop uses a calibrated delay element to compensate for propagation delays and optimizes the phase alignment speed. This feedback mechanism enables the state machine to rapidly converge to the correct phase position, significantly improving locking speed while maintaining reliable phase lock.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed CDR circuit achieves fast phase locking in less than 40 UIs, supporting a wide range of frequencies and meeting the requirements of PONs and OLTs.
Implementation Method 1
an injection locked oscillator, for receiving a voltage control signal generated according to the reference clock, and adjusting a frequency of oscillation to generate an output signal having a frequency tracked to the reference clock frequency
Implementation Method 2
a phase interpolator, coupled to the injection locked oscillator, for receiving the output clock and adjusting a phase of the output clock according to an input code to generate a sampling clock for sampling a signal
Data Source
AI summary
A clock and data recovery (CDR) circuit includes: a frequency tracking loop including an injection locked oscillator for adjusting a frequency of oscillation to generate an output signal having a frequency tracked to a reference clock frequency, and then receiving an input data signal and extracting an output clock from the input data signal; and a phase tracking circuit coupled to the frequency tracking loop. The phase tracking circuit includes: a phase interpolator for receiving the output clock and adjusting a phase of the output clock according to an input code to generate a sampling clock for sampling a signal to generate a deserialized signal; and a finite state machine, coupled to the phase interpolator, for outputting a code to the phase interpolator according to the deserialized signal of the multiplexer in order to adjust the phase of the output clock.