Burst Clock Control for Independent Core Testing in Mesh Architecture
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Solution Overview
Problem
In clock mesh architecture, it is challenging to independently test multiple circuit blocks with asynchronous clock domains, as existing technologies prevent simultaneous local injection of scan test clocks, leading to difficulties in identifying defects within integrated circuits.
Innovation Solution
A circuit with burst clock control and gating devices generates modified clock signals by allowing a preset number of clock pulses to pass through during each reference clock cycle, enabling independent testing of multiple circuit blocks through clock gating devices and multiplexing, ensuring clock signals operate in lockstep for effective scan testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock mesh technology is used with multiple clock entry points, then uniform clock distribution and low skew are achieved, but independent testing of multiple cores becomes impossible
Solution Approach 1:
The patent divides the clock mesh architecture into multiple independent clock domains, each with its own clock entry point and control logic. This segmentation allows different cores to be tested independently while maintaining the benefits of clock mesh distribution within each domain.
Solution Approach 2:
The patent introduces clock gating devices as intermediaries between the clock distribution network and individual cores. These gating devices enable selective clock injection and control, allowing independent testing of multiple cores while maintaining uniform clock distribution through the mesh architecture.
2Device complexity
If scan test clocks are injected at the base of the clock mesh, then clock distribution is simplified, but multiple cores with asynchronous clock domains cannot be tested independently
Solution Approach 1:
The patent segments the clock control function by placing clock gating devices at multiple locations within the clock mesh, rather than relying on a single base injection point. This enables independent control of asynchronous clock domains while maintaining manageable device complexity.
Solution Approach 2:
The patent adds a spatial dimension to clock injection by enabling multiple clock entry points distributed throughout the clock mesh, rather than limiting injection to a single base location. This dimensional change enables independent testing of cores with asynchronous clock domains.
3Loss of energy
If shift clock frequency is reduced for power savings, then power dissipation decreases, but testing efficiency may be impacted
Solution Approach 1:
The patent implements dynamic clock frequency control through clock gating devices that can adjust clock frequency based on testing requirements. During active testing, higher frequencies can be used for efficiency, while between tests or in low-activity modes, lower frequencies reduce power dissipation.
Solution Approach 2:
The patent uses periodic clock gating to control power dissipation, allowing clock signals to be enabled only during necessary testing operations and disabled during idle periods, thereby reducing overall power consumption while maintaining testing efficiency when active.
Data Source
AI summary
A circuit comprises a burst clock control and gating device configured to generate a modified clock signal in a test mode by allowing a preset number of clock pulses of a clock signal to go through during each clock cycle of a reference clock signal, and a plurality of clock gating devices. Each of the plurality of clock gating devices comprises a multiplexing device, wherein the modified clock signal is coupled to a selector input of the multiplexing device, and input signal generation circuitry configured to ensure the timing of the transitions on the output are derived purely from the timing of the transitions of the clock and not by the timing of the transition of the first and second inputs of the multiplexer.