Burst-Mode Clock Recovery Using Delay-Line Feedback Phase Selection
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Solution Overview
Problem
Existing clock data recovery devices in burst mode have large circuit scales and require a circuit for generating a reference clock, leading to high manufacturing costs.
Innovation Solution
A clock-generation device with a signal selector, phase delay unit, time measurement unit, and phase selector that uses feedback clocks and edge signals to reduce circuit complexity, eliminating the need for a PLL and reference clock circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a PLL including GVCO, frequency divider, phase difference detector, up-down counter, and DA converter is used for clock generation, then clock and data recovery can be performed in burst mode with rapid startup, but circuit scale becomes large and manufacturing cost increases
Solution Approach 1:
The invention extracts and removes the PLL circuit (including GVCO, frequency divider, phase difference detector, up-down counter, and DA converter) from the clock generation device. By eliminating this complex reference clock generation circuitry, the patent achieves rapid clock recovery in burst mode while significantly reducing circuit scale and manufacturing cost.
Solution Approach 2:
The clock generation device performs self-service by using the input signal itself (through edge detection) to generate the clock, rather than requiring an external reference clock from a complex PLL circuit. The edge detection circuit detects edges of the input signal and uses them directly to generate the clock, making the system self-sufficient and eliminating the need for external reference clock generation.
2Measurement precision
If an external reference clock circuit is added to generate reference clock for the clock-generation device, then clock recovery accuracy is improved, but manufacturing cost increases
Solution Approach 1:
The invention removes the external reference clock circuit from the system. By extracting this unnecessary component, the patent achieves clock recovery accuracy through edge detection of the input signal itself, without incurring the additional manufacturing cost of external reference clock generation circuitry.
Solution Approach 2:
The patent uses a simple, low-cost edge detection circuit instead of expensive external reference clock circuitry. The edge detection approach uses minimal components (inverter and delay circuit) to achieve the necessary clock recovery accuracy, representing a cost-effective solution that eliminates expensive reference clock generation hardware.
Data Source
AI summary
A clock data recovery device 1 generates a recovered clock Recovered Clock and recovered data Recovered Data based on an input signal Data In, and includes a signal selector 10, a phase delay unit 20, a time measurement unit 30, a phase selector 40, an edge detector 50, a polarity detector 60, a logic inverter 70, and a data output unit 80. The signal selector 10, the phase delay unit 20, the time measurement unit 30, and the phase selector 40 constitute a clock-generation device 1A. The phase delay unit 20 includes a plurality of cascaded delay elements 211 to 21P. The phase selector 40 selects a signal output from the delay element in a position corresponding to a unit interval time among the delay elements 211 to 21P, and outputs the signal as a feedback clock Feedback Clock.