Burst Error Correction Code Shortening for Flexible Memory ECC
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Solution Overview
Problem
Existing error correction codes for semiconductor memory devices face challenges in efficiently correcting burst errors with low complexity and flexibility for various message lengths.
Innovation Solution
A method and device for generating a burst error correction code by setting a mother code, defining syndrome sets for burst error patterns, shortening the code to ensure relative primality of syndrome sets, and designing an error correction code based on an optimal generator polynomial to maximize the length of the shortened code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BCH/RS codes are used to correct multiple errors, then error correction capability is improved, but space overhead and delay overhead increase due to long parity length
Solution Approach 1:
The patent applies partial correction by designing a code that corrects only specific frequently occurring error patterns (adjacent errors) rather than all possible multiple error patterns. This selective approach reduces the parity length from what would be required for comprehensive multiple error correction, thereby reducing space and delay overhead while maintaining practical reliability improvements.
Solution Approach 2:
The patent focuses correction capability on local error patterns (adjacent errors in physically close cells) rather than distributing correction capability uniformly across all error types. This localized approach allows the code to achieve high reliability for the most common error patterns with shorter parity, reducing overall overhead.
2Reliability
If code search methods are used to design error correction codes with specific parameters, then code performance is improved, but design complexity increases rapidly as data length increases
Solution Approach 1:
The patent performs preliminary analysis to identify the most frequently occurring error patterns (adjacent errors) before code design. By pre-determining which error patterns need correction based on physical error characteristics, the patent avoids exhaustive search for optimal codes and directly designs codes targeting these identified patterns, significantly reducing design complexity.
Solution Approach 2:
The patent changes the design parameter from comprehensive multiple error correction to targeted adjacent error correction. This parameter change allows the use of shorter parity lengths while achieving practical reliability goals, and enables systematic code construction methods rather than complex searches.
3Reliability
If existing memory error correction codes are designed to correct adjacent errors, then reliability for burst errors is improved, but flexibility for various message lengths is reduced
Solution Approach 1:
The patent introduces dynamic adaptability by designing a code construction method that can flexibly adjust to various message lengths. The code parameters and parity length can be dynamically selected based on the specific message length and required error correction capability, allowing the same code family to serve multiple applications with different requirements.
Solution Approach 2:
The patent creates a universal code design framework that can handle various message lengths and error correction requirements through a single systematic approach. The code construction method using generator polynomials and syndrome sets can be applied universally across different data lengths, making the solution versatile rather than application-specific.
Data Source
AI summary
There is provided a method for generating a burst error correction code. The method comprises: setting a mother code; defining a syndrome set corresponding to each burst error pattern for at least two burst error patterns to be corrected based on the mother code; shortening a column of a PCM (parity check matrix) of the mother code so that the defined syndrome sets are relatively prime; and designing an error correction code for the each burst error pattern based on an optimal generator polynomial maximizing a length of the shortened code within a range of a length of a parity bit of the mother code or a syndrome vector included in the syndrome set that is relatively prime.