Burst Length Control Circuit for Semiconductor Memory
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Solution Overview
Problem
Conventional burst length control in low power semiconductor memory devices is inconvenient due to the need for burst stop termination commands and disables auto-precharge mode, limiting flexibility and efficiency in burst length management.
Innovation Solution
A burst length control circuit that selectively controls burst length in an on-the-fly mode without receiving a burst stop termination command signal, using a burst length input circuit, generator circuit, adjuster, selection circuit, and counter to generate and manage burst length signals, allowing for flexible burst length selection based on write or read commands and latency, and enabling auto-precharge operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If burst stop termination (BST) scheme is used to control burst length, then burst length can be adjusted, but the system requires receiving burst stop termination commands which increases operational complexity and disables auto-precharge mode
Solution Approach 1:
The memory device autonomously determines and controls burst length based on internal address bit values without requiring external BST commands. The burst length control circuit automatically selects between BL16 and BL32 based on the least significant bit of the column address, enabling self-service burst length management that eliminates the need for external termination commands and maintains auto-precharge mode functionality
Solution Approach 2:
The system dynamically adjusts burst length based on real-time address information. The burst length control circuit responds to changing address bits during operation, automatically switching between different burst lengths (BL16/BL32) according to the current column address bit value, providing dynamic adaptability without requiring external intervention
2Manufacturing precision
If burst stop termination commands are required for burst length control, then precise burst length management is achieved, but operational efficiency decreases due to additional command processing
Solution Approach 1:
The system pre-configures burst length control logic based on address bit values before burst operations commence. The burst length control circuit is designed to automatically interpret address bits and predetermined burst length values in advance, eliminating the need for real-time command processing during burst operations and maintaining high operational efficiency while ensuring precise burst length control
3Reliability
If conventional burst length control is implemented in low power semiconductor memory devices, then basic functionality is maintained, but auto-precharge mode is disabled reducing operational flexibility
Solution Approach 1:
The burst length control circuit is designed to serve multiple functions simultaneously: it controls burst length precision, maintains auto-precharge mode capability, and supports both BL16 and BL32 operations. By integrating address-based automatic selection with predetermined burst length values, the circuit achieves multi-functionality that preserves both reliability and operational flexibility in low power semiconductor memory devices
Data Source
AI summary
A burst length control circuit includes a burst length input circuit that outputs a mode register burst length signal and a burst length on-the-fly signal, a burst length generator circuit that outputs a burst length signal, and a burst length adjuster that delays the burst length signal by a write latency time to produce a write burst length control signal. A selection circuit selects any one of the burst length signal and the write burst length control signal according to a write read command signal and an on-the-fly signal received from the burst length input circuit, and outputs a burst length control signal. A burst stop counter counts the burst length control signal according to an internal write command signal and an internal read command signal, and outputs a burst stop signal corresponding to a selected burst length.