Dynamic Burst Length Control Circuit Synchronization
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Solution Overview
Problem
Existing memory devices face synchronization issues between upstream and downstream counters due to voltage spikes or premature signal arrival, leading to incorrect burst length control, especially when the delay locked loop (DLL) has not achieved lock or when read/write signals are generated before the DLL clock is established.
Innovation Solution
A dynamic burst length control circuit that generates synchronized upstream and downstream counter clocks within the same DLL CLK domain, using a burst length control data storage circuit to hold and sequence burst length control data, ensuring that burst length control data is latched and outputted correctly by synchronizing both counters with the same delay locked loop clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the upstream and downstream counters are clocked independently with different delay paths, then each counter can operate autonomously, but synchronization errors occur when voltage spikes or signals arrive prematurely before DLL lock
Solution Approach 1:
The patent merges the clock sources for both upstream and downstream counters by deriving both clock signals from the same DLL clock domain. The upstream counter clock and downstream counter clock are both generated from delayed versions of the same DLL clock signal, ensuring they share the same reference domain and achieve automatic synchronization without requiring complex inter-counter synchronization mechanisms.
Solution Approach 2:
The DLL clock signal serves as an intermediary that mediates the timing relationship between upstream and downstream counters. By introducing this common clock intermediary with controlled delay paths, the patent ensures that both counters operate in sync with the same reference timing, preventing synchronization errors caused by independent clocking.
2Productivity
If the burst length control data is latched early before DLL lock, then the control logic can proceed, but incorrect burst length control occurs due to premature signal arrival
Solution Approach 1:
The patent applies preliminary action by pre-establishing the DLL clock domain and ensuring the clock signal is stable before allowing burst length control data to be latched. The system prepares the timing infrastructure in advance through DLL locking, and only then proceeds with data latching operations, ensuring that signals arrive at the correct time rather than prematurely.
Solution Approach 2:
The DLL provides feedback about its lock status, and this feedback is used to control when the burst length control data latching should occur. The system monitors the DLL synchronization state and enables data latching only when the DLL has achieved lock, creating a feedback-controlled mechanism that prevents premature operations.
3Adaptability or versatility
If multiple independent clock paths are used for upstream and downstream counters, then each counter can be optimized independently, but voltage spikes cause desynchronization between counters
Solution Approach 1:
The patent merges the clock paths by deriving both upstream and downstream counter clocks from the same DLL clock domain. Instead of using completely independent clock paths, the system combines them under a common reference, allowing both counters to be optimized while maintaining synchronization through their shared clock origin.
Data Source
AI summary
A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by using substantially the same latency delayed received command indications. A downstream clock generation circuit generates a clock signal from a received command indication delayed by both a delay locked loop and latency delays stored in latency control circuits. An upstream clock generation circuit generates a clock signal from the received command indication delayed by the delay locked loop and capture indications from the latency control circuits.