Burst Data Link Acquisition with Guard-Period Frequency Lock

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Solution Overview

Problem

In passive optical networks (PON), AC coupling capacitors between transmitters and receivers face issues with insufficient discharge due to inadequate host reset signals, leading to DC offset and failed signal transmission, especially during data bursts with no host reset signal, resulting in extended link negotiation periods.

Innovation Solution

Implementing a system that uses both off-chip and on-chip signaling to negotiate signal settling, allowing the transmitter and receiver to settle sequentially, with the receiver discharging AC coupling capacitors after the transmitter's DC offset has stabilized, using host and internally generated signals to control instruction timing and frequency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a host reset signal is used to discharge AC coupling capacitors, then DC offset can be removed, but the discharge time is insufficient because the reset signal is simultaneously used by both transmitter and receiver devices

Engineering Contradiction:
ImproveDC offset discharge completenessVSAvoidcapacitor discharge time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the reset signal usage into separate time slots for transmitter and receiver devices. The host reset signal first resets the transmitter, then after a predetermined time delay allowing capacitor discharge, the receiver is reset. This temporal segmentation ensures sufficient discharge time while maintaining reliable DC offset removal.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by resetting the transmitter before the receiver. The transmitter is reset first, allowing its output to stabilize and AC coupling capacitors to discharge during the predetermined time period. Only after this preliminary transmitter reset and capacitor discharge is complete does the receiver reset occur, ensuring proper signal conditions.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If sequential settling of transmitter and receiver is implemented, then signal quality improves, but link negotiation time increases

Engineering Contradiction:
Improvesignal qualityVSAvoidlink negotiation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent uses periodic action through pulsed reset signals with specific timing. The host generates periodic reset pulses that sequentially activate the transmitter and receiver at predetermined intervals. This structured periodic resetting ensures signal quality through proper settling while minimizing negotiation time through optimized pulse timing and frequency.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent changes the timing parameters of reset signals to optimize both signal quality and negotiation speed. By adjusting the predetermined time period between transmitter and receiver resets, and modifying reset signal frequency and duration, the system achieves adequate signal settling while reducing overall link negotiation time.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12500673B2Systems and methods for fast burst data link acquisition
Publication Date: 2025.12.16 SEMTECH CORP
  • US12500673B2 patent drawing
  • US12500673B2 patent drawing
  • US12500673B2 patent drawing

AI summary

A system may include a recovery circuit that may: receive a first detect signal for a first burst signal and a second detect signal for a second burst signal in a burst mode data path; receive a reference pattern signal from a continuous mode data path; generate a first lock signal locked to the first burst signal or locked to the reference pattern signal, and a second lock signal locked to the second burst signal; and output the reference pattern signal from the recovery circuit during a guard period. The frequency of the recovery circuit may be locked to the frequency of the reference pattern signal during the guard period. The guard period may start based on when the first detect signal de-asserts or when the first lock signal de-asserts. During the guard period, the recovery circuit does not output the first burst signal or the second burst signal.