Burst Access Memory Macro Scheduling for High-Frequency Operation
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Solution Overview
Problem
Existing burst access memories struggle to operate at higher clock frequencies relative to the operating voltage for a given process technology, with decoding and bit cell access delays being bottlenecks in high-speed operations.
Innovation Solution
A burst access memory is designed with a memory array comprising multiple memory macros, each divided into rows and columns, and a controller that schedules macro accesses with predefined delays, dividing each access into ordered sub-operations directed to different memory macros and columns, allowing parallel utilization and breaking down critical paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If burst access memory operates at higher clock frequencies, then productivity is improved, but use of energy increases and operation becomes unstable at given process technology
Solution Approach 1:
The memory array is divided into multiple memory macros (e.g., 4 macros) that can be accessed in parallel. Each macro contains a subset of memory cells organized in rows and columns. This segmentation allows the memory system to distribute access operations across multiple smaller units, enabling higher overall throughput without requiring each individual access path to operate at excessively high frequencies, thus managing power consumption more effectively.
Solution Approach 2:
The patent introduces a macro-level organization dimension above the traditional memory cell array. By organizing memory cells into multiple macros with local bit lines within each macro and global bit lines connecting macros, the system adds a spatial dimension to the access architecture. This allows parallel access to multiple macros simultaneously, achieving higher productivity without linearly increasing the frequency requirements of individual access paths.
2Productivity
If burst access memory operates at higher clock frequencies, then productivity is improved, but reliability deteriorates due to decoding and bit cell access delays
Solution Approach 1:
By segmenting the memory array into multiple macros, the patent reduces the decoding complexity and access delay for each individual macro. Each macro can be decoded and accessed independently with shorter critical paths, improving timing accuracy and reliability. The overall system achieves high productivity through parallel access to multiple macros rather than relying on a single high-speed access path.
Solution Approach 2:
The controller pre-charges local bit lines within each memory macro before accessing memory cells. This preliminary action prepares the bit lines in advance, reducing the actual access time and improving timing accuracy. By performing preparation operations beforehand, the system can maintain reliable timing even at higher clock frequencies.
3Speed
If conventional burst access is used, then some decoding time is saved, but speed targets cannot be met due to remaining decoding and bit cell access delays
Solution Approach 1:
The memory array is divided into multiple memory macros, each with its own local bit lines and subset of memory cells. This segmentation enables parallel access to multiple macros simultaneously, dramatically increasing access speed. The controller can issue access commands to multiple macros in parallel, achieving speed targets that would be impossible with a single monolithic memory array.
Solution Approach 2:
The patent combines multiple memory macros into a unified memory system with a common controller and global bit lines. This merging allows the system to leverage the parallel capabilities of multiple macros while presenting a single integrated interface to the processor. The combined system achieves higher productivity and clock frequency capability than any individual macro could provide alone.
Data Source
AI summary
A burst access memory comprises a memory array comprising a plurality of memory macros comprising an array of memory cells in rows and columns. The memory cells in each column are connected by at least one local bit line. The array of memory cells and local bit lines define the memory macro. A plurality of global bit lines are each connectable to several corresponding local bit lines. A controller schedules a burst access of the burst access memory by generating a plurality of macro accesses to the memory macros. The plurality of macro accesses are scheduled to start with a predefined delay in relation to each other. Each macro access is divided into a plurality of ordered sub-operations. Consecutive macro accesses are directed to different memory macros and different columns. Data for consecutive macro accesses are arranged in the different memory macros and columns to match the consecutive macro accesses.