Burst Mode Bit Line Charge Transfer for Memory Power Reduction
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Solution Overview
Problem
Power consumption in integrated circuit memory devices is high due to bit line pre-charge operations, especially in large-scale devices with many parallel sense amplifiers, which require significant current and power for pre-charging and discharging bit lines during read operations.
Innovation Solution
Implementing a method where residual charge from previously sensed bit lines is reused for pre-charging subsequent bit lines in burst read modes, using charge transfer circuitry to efficiently conserve power by predicting bit line decoding patterns and transferring charge between bit lines, thereby reducing the need for substantial pre-charge power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit line pre-charge operations are performed for each read operation, then read operations can be performed correctly, but power consumption increases significantly
Solution Approach 1:
The patent recovers residual charge from bit lines after sensing operations and reuses it for subsequent pre-charge operations. Instead of dissipating the residual charge on bit lines after each sensing operation, the system captures and stores this charge in charge storage elements, then applies it to pre-charge subsequent bit lines, thereby reducing the energy required for repeated pre-charge operations
Solution Approach 2:
The system uses the residual charge naturally present on bit lines after sensing to service the pre-charge requirement of subsequent operations. The charge that would otherwise be wasted serves a useful function in preparing the next bit line for reading, making the system partially self-sufficient in meeting its own pre-charge energy requirements
2Productivity
If a large number of bit lines are operated in parallel, then data throughput increases, but the power needed for pre-charging increases significantly
Solution Approach 1:
The patent implements charge recovery across multiple parallel bit lines, capturing residual charge from each line after sensing and storing it for reuse. This allows the system to maintain high parallel throughput while reducing the cumulative power requirement across all parallel operations by recycling charge resources across the entire parallel array
3Use of energy by moving object
If charge is transferred from previously sensed bit lines to next bit lines, then pre-charge power is reduced, but additional circuitry is required
Solution Approach 1:
The patent introduces charge storage elements as intermediary components between the sensing operation and the pre-charge operation. These storage elements temporarily hold the recovered charge and facilitate its transfer to subsequent bit lines, acting as a buffer that enables the charge reuse mechanism while isolating the complexity of the transfer operation from both the sensing and pre-charge circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces power consumption during read operations in integrated circuit memory devices, particularly in burst read and page mode operations, by leveraging charge reuse across bit lines, thereby enhancing power efficiency without impacting read sequence speed.
Implementation Method 1
Since the bit lines have relatively large capacitance, the pre-charging and discharging operations can require significant current
Data Source
AI summary
A memory device operates according to a method for reading includes pre-charging a first set of selected bit lines to a pre-charge voltage and sensing data from the cells coupled to the first set of selected bit lines. Then, residual charge is transferred from the first set of selected bit lines to corresponding members of a second set of selected bit lines. The second set of selected bit lines, having an initial charge transferred from the first set, is then pre-charged to the pre-charge voltage. The data from the cells coupled to the second set of selected bit lines it is then sensed. In embodiments described herein, the read operation occurs in a burst read mode, where a volume of data having consecutive addresses is read.