Burst-Mode CDR Circuit for Fast Optical Signal Locking

Solution Overview

Problem

In high-speed transmission communication systems, especially in passive optical networks, existing clock and data recovery (CDR) circuits struggle to quickly track data signals when switching between different optical network terminals, leading to incorrect data reception.

Innovation Solution

A CDR circuit that includes a sampling circuit for burst mode over-sampling, a selection circuit to determine data edge and center sampling results, a phase detection circuit to generate a phase locking direction, and a phase adjusting circuit to adjust the sampling timing, enabling quick locking and accurate data tracking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the clock and data recovery circuit samples the data signal with a slower speed to determine the relation between the data signal and the sampling signal, then the circuit complexity is reduced, but the tracking speed of the data signal becomes slow

Engineering Contradiction:

Improvecircuit complexityVSAvoidtracking speed

Core Design Contradiction:

Device complexityVSSpeed

Solution Approach 1:

The patent implements dynamic sampling rate adjustment by switching between first sampling rate (higher) and second sampling rate (lower) based on signal conditions. The sampling circuit dynamically changes its operation mode to optimize both tracking speed and circuit complexity, using higher sampling rate when rapid tracking is needed and lower sampling rate when stability is sufficient.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the sampling rate parameter from a fixed value to a variable that can switch between two distinct values. This parameter change allows the system to adapt to different operational requirements, achieving fast initial acquisition with higher sampling rate and energy-efficient operation with lower sampling rate.

Inventive Principle:

Principle #35Parameter changes

2Use of energy by moving object

If the clock and data recovery circuit operates with a slower sampling speed, then the energy consumption is reduced, but the data signal cannot be tracked quickly when switching between different optical network terminals

Engineering Contradiction:

Improveenergy consumptionVSAvoidtracking time

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent implements dynamic sampling rate adjustment by switching between first sampling rate (higher) and second sampling rate (lower) based on signal conditions. The sampling circuit dynamically changes its operation mode to optimize both tracking speed and circuit complexity, using higher sampling rate when rapid tracking is needed and lower sampling rate when stability is sufficient.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the sampling rate parameter from a fixed value to a variable that can switch between two distinct values. This parameter change allows the system to adapt to different operational requirements, achieving fast initial acquisition with higher sampling rate and energy-efficient operation with lower sampling rate.

Inventive Principle:

Principle #35Parameter changes

3Speed

If the sampling rate is increased to track the data signal quickly, then the tracking speed is improved, but the circuit complexity and energy consumption increase

Engineering Contradiction:

Improvetracking speedVSAvoidcircuit complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent implements dynamic sampling rate adjustment by switching between first sampling rate (higher) and second sampling rate (lower) based on signal conditions. The sampling circuit dynamically changes its operation mode to optimize both tracking speed and circuit complexity, using higher sampling rate when rapid tracking is needed and lower sampling rate when stability is sufficient.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the sampling rate parameter from a fixed value to a variable that can switch between two distinct values. This parameter change allows the system to adapt to different operational requirements, achieving fast initial acquisition with higher sampling rate and energy-efficient operation with lower sampling rate.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12267076B2Signal receiving apparatus, clock and data recovery circuit and clock and data recovery method thereof

Publication Date: 2025.04.01 REALTEK SEMICON CORP

AI summary

The present disclosure discloses a clock and data recovery circuit. A sampling circuit performs burst mode over-sampling on an input analog data signal according to a sampling timing in a burst mode to generate over-sampling results. A selection circuit determines neighboring two of the over-sampling results having opposite logic states in the burst mode to select data edge sampling results and data center sampling results interlaced with each other and having the same time period with input analog data signal from the over-sampling results accordingly to be output sampling results. A phase detection circuit performs phase detection according to the output sampling result to generate a phase locking direction. A phase adjusting circuit adjusts the sampling timing of the sampling circuit according to the phase locking direction to track the input analog data signal.