Burst-Mode Decision Feedback Equalization for Gapped Data Bursts

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Solution Overview

Problem

Decision feedback equalizers (DFEs) are limited in their application to bursty signaling systems due to the requirement of uninterrupted symbol transmission for channel-response estimation, leading to suboptimal performance in bursty transmission profiles.

Innovation Solution

The implementation of burst-mode decision feedback equalization, which dynamically seeds the decision feedback equalizer using gap measurements between burst transmissions, enabling improved signaling performance even in bursty transmission profiles by adjusting decision feedback signals and equalization coefficients based on detected gaps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If decision feedback equalizer (DFE) is used to estimate channel-response, then signaling margin is increased and bit error rates are reduced, but uninterrupted symbol transmission is required which limits application in bursty signaling systems

Engineering Contradiction:
Improvebit error rateVSAvoidapplicability to bursty signaling systems
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies preliminary action by pre-seeding the DFE tap memory with predetermined seed values before burst transmissions occur. This allows the DFE to be quickly initialized and become operational during burst mode without requiring continuous training sequences, thereby enabling reliable channel-response estimation in bursty signaling systems while maintaining low bit error rates

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamics by making the DFE operational state configurable between continuous mode and burst mode. The system dynamically adapts its behavior based on transmission conditions, allowing it to function effectively in both uninterrupted and bursty signaling environments, thus resolving the contradiction between reliability improvement and adaptability to different signaling patterns

Inventive Principle:
Principle #15Dynamics

2Measurement precision

If DFE requires uninterrupted symbol transmission for channel-response estimation, then accurate equalization is achieved, but performance deteriorates in bursty transmission profiles with gaps between bursts

Engineering Contradiction:
Improvechannel-response estimation accuracyVSAvoidsignaling performance in bursty systems
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent uses preliminary action by pre-loading the DFE tap memory with seed values that represent expected channel conditions before burst transmissions. This preliminary initialization allows the DFE to maintain accurate channel-response estimation during burst mode operation without requiring continuous training sequences, thereby preserving measurement precision while enabling productivity in bursty systems

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies copying by using predetermined seed values that replicate expected channel-response characteristics. These seed values serve as copies of anticipated channel conditions, allowing the DFE to quickly reconstruct accurate equalization parameters during burst transmissions without needing to continuously measure the actual channel, thus maintaining precision while improving bursty system performance

Inventive Principle:
Principle #26Copying

Data Source

PatentEP3883129A1Burst-tolerant decision feedback equalization
Publication Date: 2021.09.22 RAMBUS INC
  • EP3883129A1 patent drawingFigure 1~2
  • EP3883129A1 patent drawingFigure 3
  • EP3883129A1 patent drawingFigure 4~6

AI summary

A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.