Burst-Mode Signal Conversion With Digital Phase Delay Compensation
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Solution Overview
Problem
Conventional automatic test equipment (ATE) for high-speed devices in the GHz frequency range is limited by jitter in stimulus and conversion clock signals, leading to high costs and development efforts for ultra-low jitter clocks, and existing circuits require multiple phase-locked loops (PLLs) that consume board space and have long settling times.
Innovation Solution
A circuit that includes a processor, converter, phase comparator, and digital signal processor to determine and compensate for phase differences between synchronizing and converter clock signals, allowing for efficient signal conversion in burst mode without the need for multiple PLLs, using a phase-to-digital converter and fractional delay filter to align signal edges and apply delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLLs are used for clock synchronization, then phase locking is achieved, but board space consumption increases and settling time is prolonged
Solution Approach 1:
The patent combines the phase detection and delay adjustment functions into a single integrated circuit module, eliminating the need for separate PLL components. This merging of functions reduces board space while maintaining phase synchronization capability through the delay element that directly adjusts signal timing based on phase difference detection.
Solution Approach 2:
The patent extracts the essential phase synchronization function from the complex PLL architecture, retaining only the critical components (phase detector and delay element) needed for phase alignment. This extraction eliminates unnecessary PLL components, reducing board space consumption while preserving the core phase locking functionality.
2Reliability
If conventional PLLs are used for clock synchronization, then phase locking is achieved, but settling time before each burst increases
Solution Approach 1:
The patent performs preliminary phase difference detection and delay adjustment setup before each burst operation. The delay element is pre-configured with the measured phase difference, allowing immediate synchronization at the start of each burst without requiring extended settling time. This preliminary preparation eliminates the prolonged settling period associated with conventional PLLs.
Solution Approach 2:
The patent implements a dynamic delay adjustment mechanism that can be rapidly reconfigured between bursts. The delay element responds quickly to phase difference changes, enabling fast settling time. This dynamic responsiveness allows the system to adapt to phase variations without the long settling times characteristic of traditional PLL architectures.
3Reliability
If multiple PLLs are used for each channel, then clock synchronization is achieved, but device complexity and cost increase
Solution Approach 1:
The patent implements a universal phase synchronization module that can be shared across multiple channels. The delay element and phase detection mechanism serve all channels, eliminating the need for dedicated PLLs in each channel. This multi-functional approach reduces device complexity and component count while maintaining synchronization across all channels.
Solution Approach 2:
The patent merges the clock synchronization function across multiple channels into a single integrated module. Instead of implementing separate PLLs for each channel, the system uses one phase detector and shared delay elements to synchronize all channels, significantly reducing device complexity and component requirements.
4Reliability
If PLLs with special external components are used, then low jitter is achieved, but manufacturing cost and development effort increase
Solution Approach 1:
The patent replaces expensive, specialized PLL components with inexpensive, standard digital logic elements and delay circuits. The delay element can be implemented using simple digital buffers or FIFO structures that are readily available and cost-effective. This substitution dramatically reduces manufacturing cost and development effort while achieving the required jitter performance through precise digital delay control.
Solution Approach 2:
The patent replaces the analog/RF-based PLL mechanism with a digital signal processing approach. Instead of using analog phase-locked loop circuits with external components, the system uses digital phase detection and programmable delay elements. This substitution eliminates the need for expensive external PLL components and simplifies manufacturing.
Data Source
AI summary
An electronic circuit for converting a signal between digital and analog in a burst mode, including a processor configured to utilize a synchronizing clock signal, a converter configured to convert a signal data between digital and analog using a converter clock signal, a phase comparator configured to determine a phase relationship between the synchronizing clock signal and the converter clock signal, and a digital signal processor coupled to the phase comparator and configured to receive an information about the phase relationship, wherein the digital signal processor is configured to apply a delay to the signal data being exchanged between the processor and. The synchronizing clock signal and the converter clock signal have a predetermined frequency relationship.