Burst Mode Controller for Synchronous Rectifier Light-Load Efficiency

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Solution Overview

Problem

Resonant converters face inefficiencies under light-load conditions due to constant losses from conduction and switch losses, which are exacerbated by the need for a specific magnetizing current for soft-switching, resulting in lower light-load efficiency compared to heavy-load efficiency.

Innovation Solution

A burst mode controller for synchronous rectification circuits that delays the generation of synchronous rectification driving signals and turns them off ahead of the ending of the last operating period to avoid energy transfer back, optimizing the driving of synchronous rectifiers and minimizing losses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If resonant converters operate under light-load condition with specific magnetizing current for soft-switching, then soft-switching is achieved, but conduction loss and switch loss increase resulting in lower light-load efficiency

Engineering Contradiction:
Improvesoft-switchingVSAvoidconduction loss and switch loss
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies periodic action by implementing burst mode control where the converter operates in intermittent cycles rather than continuously. During light-load conditions, the converter alternates between active switching periods and idle periods, allowing the magnetizing current to decay below the soft-switching threshold during idle time. This periodic operation reduces average conduction and switch losses while maintaining soft-switching during active periods, thereby improving light-load efficiency.

Inventive Principle:
Principle #19Periodic action

2Device complexity

If synchronous rectifiers are turned on at the same timing as primary switches, then simple control is achieved, but energy transfers back from secondary to primary side causing large resonant current and increasing power loss

Engineering Contradiction:
Improvecontrol timingVSAvoidpower loss
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The patent applies preliminary action by advancing the turn-off timing of synchronous rectifiers relative to the primary switches. Specifically, the synchronous rectifiers are turned off one operating period ahead of the ending of the last operating period of the driving signal of the first switch. This preliminary turn-off prevents the resonant current from becoming negative and transferring energy back to the primary side, thereby reducing power loss while maintaining relatively simple control implementation.

Inventive Principle:
Principle #10Preliminary action

3Stability of the object's composition

If resonant converter operates continuously under light-load condition, then steady operation is maintained, but constant losses result in lower efficiency compared to heavy-load efficiency

Engineering Contradiction:
Improvesteady operationVSAvoidconstant losses
Core Design Contradiction:
Stability of the object's compositionVSLoss of energy

Solution Approach 1:

The patent applies periodic action by implementing burst mode control that alternates between active and idle periods during light-load conditions. Instead of continuous operation, the converter operates in bursts where it maintains steady operation during active periods (with proper synchronous rectifier timing) and enters idle periods where losses are minimized. This periodic operation pattern reduces average constant losses while maintaining system stability and readiness for load changes.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8031489B2Synchronous rectification circuit having burst mode controller and controlling method thereof
Publication Date: 2011.10.04 DELTA ELECTRONICS INC(CN)
  • US8031489B2 patent drawing
  • US8031489B2 patent drawing
  • US8031489B2 patent drawing

AI summary

The configuration of a synchronous rectification circuit and a controlling method thereof are provided. The proposed circuit includes a converter including a first switch and a first synchronous rectifier, and a burst mode controller including a logic process module performing one of functions of delaying one of a non-integer and at least one operating periods to generate a synchronous rectification driving signal of the first synchronous rectifier counting from a beginning of a first pulse of a driving signal of the first switch during a working time of a burst period, and turning off the synchronous rectification driving signal of the first synchronous rectifier by one of the non-integer operating period and the at least one operating period ahead of an ending of a last operating period of the driving signal of the first switch during the working time of the burst period.