Burst-Mode Optical Receiver for Fast Bias and Clock Acquisition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing burst-mode optical receivers take a significant amount of time to acquire DC-bias signal levels and perform clock-recovery operations, hindering the development of energy-proportional communication links that can rapidly turn on and off to reduce power consumption in data centers.
Innovation Solution
The optical receiver design incorporates a feed-forward circuit for DC-bias signal acquisition and a clock-recovery circuit with a delay-locked loop and bang-bang clock-and-data-recovery mechanism, using a passive resistor instead of a transimpedance amplifier to quickly adjust to varying optical signal powers and perform flash-oversampling for rapid clock recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional feedback-based DC-bias acquisition is used, then the receiver can acquire DC-bias signal levels, but it requires a significant amount of time during initial calibration
Solution Approach 1:
The patent applies preliminary action by using a feed-forward circuit that pre-acquires the DC-bias signal level from the incoming optical signal before the main receiver operation begins. This allows the system to have the DC-bias information ready in advance, eliminating the time-consuming feedback-based calibration process while ensuring accurate DC-bias levels are established for rapid receiver startup.
2Loss of time
If traditional clock recovery methods are used, then the receiver can extract clock signals, but it requires a significant amount of time for initial calibration and clock recovery operations
Solution Approach 1:
The patent applies preliminary action by using flash-oversampling to capture multiple samples of the incoming signal at different phases during the initial calibration period. This preliminary sampling allows the system to quickly identify the optimal sampling phase and establish an accurate clock signal before normal operation begins, significantly reducing clock recovery time while maintaining precision.
Solution Approach 2:
The patent applies periodic action through the use of a delay-locked loop (DLL) that generates multiple equally spaced phases by periodically delaying a reference signal. This periodic phase generation allows the system to efficiently search for and lock onto the correct clock phase, enabling rapid and accurate clock recovery without requiring time-consuming iterative adjustments.
3Speed
If a transimpedance amplifier is used to convert photocurrent to voltage, then the conversion can be performed, but it slows down the receiver's ability to rapidly adjust to varying optical signal powers
Solution Approach 1:
The patent applies the taking out principle by removing the transimpedance amplifier from the receiver circuit and using only a passive resistor for the photocurrent-to-voltage conversion. This extraction of the complex active component simplifies the circuit and removes the bandwidth-limiting feedback mechanism, allowing the receiver to rapidly respond to power variations while maintaining the essential conversion function through the simpler passive resistor element.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables rapid extraction of DC-bias signal levels and clock recovery, facilitating energy-proportional communication links by minimizing startup delays and maintaining stability during data transmission, thus reducing power consumption in data centers.
Implementation Method 1
a photodiode that converts an optical signal into the photocurrent
Data Source
AI summary
An optical receiver receives a photocurrent from a photosensor and uses a transimpedance element to convert the photocurrent into an input signal. Next, an amplifier amplifies the input signal to produce an amplified input signal. At the same time, a clock-recovery circuit generates a clock signal, which is used to clock the amplified input signal to produce a receiver output. During an initial-calibration operation, the clock-recovery circuit phase-aligns a locally generated reference signal with transitions in the amplified input voltage signal to produce the clock signal by: feeding the reference signal through a delay-locked loop to produce a set of equally spaced phases; using the set of equally spaced phases to sample a preamble in the amplified input voltage signal to detect a crossing point; choosing a corresponding phase from the set of equally spaced phases based on the crossing point; and using the chosen phase to produce the clock signal.