Burst Order Control Circuit Timing Margin Stabilization
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Solution Overview
Problem
Conventional burst order control circuits in semiconductor devices face instability due to inadequate timing margin and loading differences between rising and falling burst signals, leading to deteriorated duty and skew characteristics.
Innovation Solution
A burst order control circuit with a burst signal generating unit that generates and toggles rising and falling burst signals based on a seed column address and latency signals, and a repeater unit that shifts these signals to ensure proper alignment and timing, including a delayed clock mechanism to maintain stability and prevent signal deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the burst signal is toggled at every clock cycle to achieve fast data output, then the productivity is improved, but the timing margin becomes insufficient leading to circuit instability
Solution Approach 1:
The patent applies preliminary action by generating the burst signal earlier in the clock cycle and using delay elements to pre-adjust the timing. The burst signal is generated at CL-3 and delayed through multiple stages to reach the pipe latch at the appropriate time, ensuring sufficient timing margin while maintaining high data output speed.
Solution Approach 2:
The patent uses delay elements and repeater units as intermediary components between the burst signal generation and the pipe latch. These intermediaries buffer and condition the signals, providing adequate timing margin and preventing direct conflicts between fast toggling and circuit stability requirements.
2Adaptability or versatility
If the rising and falling burst signals are generated with different loading conditions to match data requirements, then the adaptability is improved, but the duty and skew characteristics deteriorate
Solution Approach 1:
The patent applies local quality by providing different delay paths and loading conditions for rising and falling burst signals at specific stages. The first and second rising burst signals receive different treatments from the first and second falling burst signals, allowing each to be optimized for its specific data output requirements while maintaining overall signal integrity.
Solution Approach 2:
The patent segments the burst signal generation into multiple independent paths: first rising burst signal path, second rising burst signal path, first falling burst signal path, and second falling burst signal path. Each path can be independently optimized with appropriate delay elements and loading conditions, preventing mutual interference and maintaining precise duty and skew characteristics.
Data Source
AI summary
A burst order control circuit includes a burst signal generating unit configured to receive a seed column address and to generate a first rising burst signal, a second rising burst signal, a first falling burst signal and a second falling burst signal in response to the seed column address, and a repeater unit configured to transfer the first rising burst signal, the second rising burst signal, the first falling burst signal and the second failing burst signal to a pipe latch.