Burst Phase Detection Circuit for Multi-Rate Data Stream Locking
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Solution Overview
Problem
In bursty data systems, existing phase detection methods are inefficient due to long locking times and require costly custom circuitry or lengthy preambles, limiting the ability to upgrade BCDRs without upgrading all ONUs, and fail to support diverse line rates and fractional frequencies.
Innovation Solution
A circuit and method featuring a programmable clock generator and burst phase detector that can operate with multiple clock signals, allowing for quick phase detection and synchronization with zero or negative locking time, supporting diverse line rates and fractional frequencies without the need for custom high-speed electronics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional phase detection methods are used in bursty data systems, then the receiver can detect the phase of the data stream, but the locking time is long which limits system upgrade flexibility
Solution Approach 1:
The patent implements a dynamic clock selection mechanism where the BCDR can adaptively switch between multiple clock signals (e.g., 1.25 GHz, 2.5 GHz, 10.315 GHz) based on the detected line rate. This dynamic adaptability allows the system to quickly synchronize with incoming data streams at various speeds without requiring lengthy preambles or custom circuitry for each specific rate, thereby reducing locking time while maintaining versatility.
Solution Approach 2:
The BCDR is designed with universal functionality to handle multiple line rates and clock frequencies using a single integrated circuit. By incorporating a programmable clock generator and multiple phase-locked loops (PLLs) that can be configured for different frequencies, the system achieves multi-functionality, eliminating the need for separate custom circuitry for each line rate and enabling flexible network upgrades.
2Speed
If custom high-speed electronics are used to reduce locking time, then phase detection speed improves, but the cost and device complexity increase
Solution Approach 1:
The patent utilizes parameter changes by configuring existing PLL components with different frequency dividers and clock selection parameters to support multiple line rates. Instead of designing custom high-speed electronics for each frequency, the system changes operational parameters (division ratios, clock sources) of standard components to achieve fast phase detection across various speeds, thereby maintaining simplicity while improving performance.
Solution Approach 2:
The system employs multiple phase-locked loop copies that can be selectively activated based on the detected line rate. Each PLL copy is pre-configured for a specific frequency range, allowing the system to quickly switch to the appropriate copy rather than using complex custom circuitry. This approach achieves fast phase detection using standardized, replicated components rather than expensive custom designs.
3Productivity
If all ONUs are upgraded simultaneously to support faster BCDR, then the system can operate at higher line rates, but the upgrade cost and coordination complexity increase
Solution Approach 1:
The BCDR incorporates dynamic clock selection and line rate detection capabilities that allow it to automatically adapt to the capabilities of connected ONUs. The system can dynamically switch between supported line rates (1.25 Gbps, 2.5 Gbps, 10.315 Gbps) based on ONU capabilities, enabling gradual network upgrades where newer BCDRs can operate at higher rates with capable ONUs while maintaining compatibility with older ONUs at lower rates.
Solution Approach 2:
The BCDR is designed as a universal interface that can communicate with ONUs of different generations and capabilities. By integrating multiple clock generators and PLLs that support various standard line rates, the system provides backward compatibility while enabling forward upgrades. This multi-functional design allows telecom operators to upgrade BCDRs incrementally without requiring simultaneous ONU replacements across the entire network.
Data Source
AI summary
A circuit for processing a data stream is described. The circuit comprises a burst phase detector configured to receive a data input signal; a clocking circuit coupled to the burst phase detector, wherein the clocking circuit is configured to receive a delayed data input signal and to receive a data stream phase signal and a data stream detect signal; and a programmable clock generator configured to receive a plurality of clock signals; wherein a selected clock signal of the plurality of clock signals is generated by the programmable clock generator and provided to the burst phase detector and the clocking circuit.