Burst Register Sampling Using FIFO Memory for At-Speed Debug
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Solution Overview
Problem
Testing and debugging of ASIC designs emulated on programmable logic devices, such as FPGAs, can be time-consuming and often occur at a speed lower than the targeted real-time operation speed, hindering efficient validation and error correction.
Innovation Solution
Implementing burst sampling techniques that allow continuous data capture from user registers at the clock speed of the programmable logic device, utilizing FIFO operations to sample data over multiple clock cycles, enabling at-speed debugging and error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional testing methods are used for ASIC designs emulated on programmable logic devices, then debugging can be performed, but the testing speed is lower than the targeted real-time operation speed
Solution Approach 1:
The patent implements continuous data capture from user registers at the full clock speed of the programmable logic device using FIFO buffers. The sampling mechanism operates continuously without interruption or deceleration of the emulation process, allowing debug data to be captured at the same speed as the targeted real-time operation speed while maintaining uninterrupted emulation execution
Solution Approach 2:
The patent introduces FIFO (First-In-First-Out) buffers as an intermediary mechanism between the user registers and the debug interface. These buffers decouple the high-speed data production from the debug data retrieval process, enabling the emulation to run at full speed while debug data is systematically captured and made available for analysis without slowing down the overall process
2Reliability
If emulation is performed at full clock speed, then real-time operation validation is achieved, but continuous data capture for debugging becomes difficult
Solution Approach 1:
The FIFO buffers serve as an intermediary that simplifies debugging at full speed by automatically capturing and organizing data from user registers. This intermediary structure handles the complexity of high-speed data capture, presenting a simplified interface for debugging while maintaining full clock speed operation and ensuring reliable real-time validation
Solution Approach 2:
The sampling mechanism automatically captures data from user registers without requiring external intervention or manual triggering. The system self-manages the data capture process at full clock speed, with the FIFO buffers autonomously handling data storage and retrieval, thereby reducing debugging complexity while maintaining validation accuracy
Data Source
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AI summary
Systems and methods described herein may relate to burst sampling of an integrated circuit device. Such a system may include a first logic access block (26A) including a data register (74A) and a second logic access block (26B) including a memory column (52A). The memory column may be configurable to operate as a First In, First Out, FIFO, user lookup table, LUT, mode, or as user random access memory, RAM. The memory column (52A) may store data sampled from the data register (74A) for any number of clock cycles and the data may be sampled at the speed of a clock of a device under test, DUT.