Burst Sampling FIFO for At-Speed User Register Debug

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Solution Overview

Problem

Testing ASIC designs emulated on programmable logic devices, such as FPGAs, is time-consuming and often conducted at speeds lower than the intended real-time operation, hindering efficient debugging and validation.

Innovation Solution

Implementing burst sampling techniques that allow continuous data capture from user registers at the clock speed of the programmable logic device, using FIFO operations to sample data across multiple clock cycles, enabling at-speed debugging without slowing down the emulation process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ASIC design emulation is performed on programmable logic devices, then design validation is enabled, but testing speed is reduced below real-time operation speed

Engineering Contradiction:

Improvedesign validation accuracyVSAvoidtesting speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent pre-configures memory columns to operate as FIFO buffers before burst sampling begins. This preliminary setup allows the sampling mechanism to immediately capture data at full clock speed without requiring slow sequential read operations, thus resolving the contradiction between validation accuracy and testing speed

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements continuous burst sampling that captures data across multiple clock cycles without interruption. This continuous operation maintains real-time testing speed while accumulating sufficient validation data, eliminating the need to slow down the emulation process for discrete sampling operations

Inventive Principle:

Principle #20Continuity of useful action

2Loss of information

If traditional sampling methods are used for debug operations, then data capture is enabled, but the process requires slowing down the emulation speed

Engineering Contradiction:

Improvedata capture capabilityVSAvoiddebugging efficiency

Core Design Contradiction:

Loss of informationVSProductivity

Solution Approach 1:

The patent introduces FIFO buffers as an intermediary between the data registers and the sampling mechanism. These buffers temporarily hold captured data, allowing the sampling operation to proceed independently at full speed without requiring the main emulation process to slow down, thus maintaining both data capture capability and debugging efficiency

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent divides the data capture process into separate stages: continuous burst sampling in the first clock cycles followed by sequential read operations in subsequent cycles. This segmentation allows the critical sampling phase to operate at full speed while the less time-sensitive read phase can proceed sequentially, resolving the contradiction between information capture and productivity

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12197360B2At-speed burst sampling for user registers

Publication Date: 2025.01.14 ALTERA CORP

AI summary

Systems and methods described herein may relate to burst sampling of an integrated circuit device. Such a system may include a first logic access block including a data register and a second logic access block including a memory column. The memory column may be configurable to operate as a First In, First Out (FIFO), user lookup table (LUT) mode, or as user random access memory (RAM). The memory column may store data sampled from the data register for any number of clock cycles and the data may be sampled at the speed of a clock of a device under test (DUT).