Burst Sequence Control in Memory Decoder Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In memory devices, accessing multiple words in parallel to speed up operations can lead to performance penalties due to the need to access extra words from multiple memory arrays, even when they are not needed, and existing redundancy logic does not efficiently handle defective memory cells.
Innovation Solution
A decoder circuit responsive to a burst sequence control signal, which uses a logic circuit to manage select lines and a multi-valued fuse circuit to output signals for redundancy evaluation, allowing efficient access to memory locations and redirecting accesses from defective cells to redundant cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple memory arrays are accessed in parallel to speed up operations, then memory operation speed is improved, but performance penalties occur due to accessing extra words that are not needed
Solution Approach 1:
The patent implements dynamic control of memory array access through a burst sequence control signal that adaptively enables or disables additional array accesses based on whether defective memory cells are detected. The system transitions from a static parallel access mode to a dynamic mode where the number of active arrays is adjusted in real-time, allowing the system to maintain high speed when all cells are functional while avoiding waste when defects are present.
Solution Approach 2:
The system changes the operational parameters of the memory interface by modifying how column select signals are generated and propagated to different memory arrays. Through multi-valued fuse circuits and logic circuits, the patent dynamically alters the selection parameters sent to each array, enabling selective activation of arrays based on the presence of defective cells, thereby optimizing the balance between speed and effective productivity.
2Reliability
If redundancy logic is implemented to handle defective memory cells, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent uses copying by implementing multiple column decoder circuits that are replicas of each other, each associated with a different memory array. Instead of creating complex unique logic for each redundancy scenario, the system copies the basic decoder functionality across multiple arrays and uses simple control signals to select which copies are active. This approach maintains reliability through redundancy while keeping the complexity of individual components low.
Solution Approach 2:
The column select signals and decoder circuits are designed to serve multiple functions: they can address valid memory cells in any array, address defective cells that need redirection, and dynamically enable or disable arrays based on defect presence. This multi-functionality reduces the need for specialized complexity in the redundancy logic, as the same hardware structures perform both normal access and defect-handling operations.
Data Source
AI summary
A decoder circuit, responsive to a burst sequence control signal, for accessing a memory location in a memory array. The decoder circuit receives an address signal and outputs a plurality of first select lines. Logic circuitry receives these first select lines and a burst sequence control signal and outputs a plurality of second select lines. When the bust sequence control signal is unasserted, the logic circuitry passes through to the plurality of second select lines the signals received on the plurality of first select lines. When the burst sequence control signal is asserted, the logic circuitry performs a logical operation on the signals received on the plurality of first select lines and outputs the result on the plurality of second select lines.