Bus Address Channel Multiplexing for Write Latency
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Solution Overview
Problem
Modern processing systems face challenges in reducing write latency and increasing write bandwidth due to the limitations of standardized bus architectures with separate read, write, and address channels.
Innovation Solution
The proposed solution involves a bus architecture that uses a 32-bit address channel and 64-bit write channel, with control signals like Address/Data and Transfer Attribute to facilitate simultaneous transmission of addresses and payloads, allowing for concurrent write operations and improved data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate read, write and address channels are used in standardized bus architectures, then channel independence and standardization are achieved, but write latency increases and write bandwidth decreases
Solution Approach 1:
The patent merges the address channel and write channel into a single multiplexed channel. The address channel is used to transmit both address information and write payload data, eliminating the need for a separate write channel. This combining of channels reduces the number of sequential operations required for write transactions, thereby reducing write latency while maintaining channel independence through logical separation of functions.
Solution Approach 2:
The address channel is designed to serve multiple functions: transmitting address information during read operations and transmitting write payload data during write operations. This multi-functionality allows the same physical channel to handle different types of data traffic at different times, increasing write bandwidth by utilizing the channel more efficiently without requiring additional dedicated write channels.
2Adaptability or versatility
If separate read, write and address channels are used in standardized bus architectures, then channel independence and standardization are achieved, but write bandwidth decreases
Solution Approach 1:
The patent merges the address channel and write channel into a single multiplexed channel. The address channel is used to transmit both address information and write payload data, eliminating the need for a separate write channel. This combining of channels reduces the number of sequential operations required for write transactions, thereby reducing write latency while maintaining channel independence through logical separation of functions.
Solution Approach 2:
The address channel is designed to serve multiple functions: transmitting address information during read operations and transmitting write payload data during write operations. This multi-functionality allows the same physical channel to handle different types of data traffic at different times, increasing write bandwidth by utilizing the channel more efficiently without requiring additional dedicated write channels.
3Device complexity
If address and payload are transmitted sequentially over separate channels, then channel functionality is simplified, but transmission efficiency decreases
Solution Approach 1:
The patent implements dynamic channel multiplexing where the address channel's function changes based on the operation type. Control signals dynamically switch the channel between address transmission mode and payload transmission mode. This dynamic allocation allows the channel to be optimized for different functions at different times, improving transmission efficiency without permanently complicating the channel structure.
Solution Approach 2:
The bus protocol uses periodic alternation between address phase and payload phase during write operations. The address channel first transmits address information in an initial phase, then subsequently transmits payload data in a later phase within the same operational cycle. This periodic switching between functions allows efficient use of the channel while maintaining clear separation of concerns through time-division multiplexing.
Data Source
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AI summary
A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to select between the first and third channels to write a payload to the receiving device.