Bus Address Verification via Parity Signal Suppression
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Solution Overview
Problem
Data communications over computer buses, such as I2C buses, lack error detection and correction, leading to unstable data transfers due to interference and noise, which can result in incorrect address recognition and subsequent data transmission errors.
Innovation Solution
Implement address verification methods where receiving bus nodes check the parity signal and address signal for matching and integrity, suppressing acknowledgments if the parity signal is unexpected, and retransmitting signals if interference is detected, ensuring accurate data communication by matching addresses and expected parity values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection and correction are added to bus communications, then data transfer reliability is improved, but device complexity increases
Solution Approach 1:
The patent changes the parameter of error detection from complex algorithms to simple parity bit verification. By transmitting a parity signal alongside the address signal and verifying it at the receiving end, the system achieves error detection without adding complex error correction mechanisms, thus improving reliability while maintaining protocol simplicity
Solution Approach 2:
The patent introduces an acknowledgment signal as an intermediary mechanism between address transmission and data transfer. The receiving node sends an acknowledgment only after successfully verifying both the address match and parity signal, providing indirect error detection that ensures reliable communication without requiring complex direct error correction protocols
2Measurement precision
If address verification with parity checking is implemented, then measurement precision of address recognition is improved, but device complexity increases
Solution Approach 1:
The patent segments the address transmission process into two independent verification components: address matching and parity verification. This segmentation allows each component to be processed separately with simple logic, improving address recognition accuracy while avoiding the complexity of integrated error correction systems
Solution Approach 2:
The patent creates a simplified copy of error detection functionality using parity bits instead of full error correction codes. The parity signal is a minimal copy that provides verification capability without the complexity of complete error detection and correction algorithms, thus improving measurement precision while limiting device complexity
3Loss of information
If retransmission protocol is added, then loss of information is reduced, but loss of time increases
Solution Approach 1:
The patent implements a feedback mechanism where the receiving node sends an acknowledgment signal back to the sending node only when both address matching and parity verification succeed. This feedback loop enables selective retransmission only when errors are detected, reducing information loss while minimizing time loss by avoiding unnecessary retransmissions of correct data
Solution Approach 2:
The patent applies partial action by implementing error detection only at the address verification stage rather than throughout the entire data transmission process. This partial verification approach reduces information loss for address-related errors while minimizing time loss by not over-engineering the solution with comprehensive error correction for all data types
Data Source
AI summary
Address verification on a bus, the bus connecting a plurality of receiving bus nodes and one or more sending bus nodes, the bus providing communication among the bus nodes, including: receiving, by a receiving bus node over the bus, a parity signal and an address signal, the address signal identifying an address of a target receiving bus node; determining, by the receiving bus node, whether the address of the target receiving bus node matches an address of the receiving bus node; responsive to determining that the address of the target receiving bus node matches the address of the receiving bus node, determining, by the receiving bus node, whether the parity signal is an expected parity signal; and responsive to determining that the parity signal is not the expected parity signal, suppressing, by the receiving bus node, an acknowledgment of receipt of the address signal.