Bus Agent Store Latency Reduction in SMP Systems
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Solution Overview
Problem
In symmetrical multiprocessor systems, inefficiencies arise due to the need for multiple retries and Kill requests when multiple nodes compete for ownership of shared cache lines, leading to increased store latency and reduced system performance.
Innovation Solution
Implementing intelligent bus agents that monitor ownership requests and determine if they are winners or losers, allowing winners to perform data modifications without Kill requests and losers to degrade their requests to 'Read With Intent to Modify' without retrying, thus eliminating the need for Kill requests and retries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple nodes compete for ownership of shared cache lines using traditional arbitration, then cache coherence is maintained, but store latency increases due to multiple retries and Kill requests
Solution Approach 1:
The patent applies preliminary action by having the winning node proactively send a Kill request to invalidate cache lines in other nodes before the losing nodes can attempt their ownership requests. This preemptive invalidation prevents the need for multiple retries and reduces store latency while maintaining cache coherence.
2Device complexity
If the arbiter ensures no two commands to the same address are active simultaneously, then system complexity in components is reduced, but store latency increases due to sequential processing
Solution Approach 1:
The arbiter sends a Kill request as a preliminary action immediately after determining the winner, before processing subsequent ownership requests. This allows the system to maintain simple sequential arbitration logic while reducing the overall latency by proactively invalidating cache lines before other nodes need to retry their requests.
Data Source
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AI summary
A system and method for reducing store latency in symmetrical multiprocessor systems are provided. Bus agents are provided which monitor reflected ownership requests (Dclaims) to determine if the reflected Dclaim is its own Dclaim. If so, the bus agent determines that it is the winner of the ownership request and can immediately perform data modification using its associated local cache. If the bus agent determines that the reflected Dclaim does not match its own Dclaim, it determines that it is the loser of the ownership request and invalidates the corresponding cache line in its own local cache. The loser bus agent may then send a Read With Intent to Modify request to obtain the data from another cache and place it into its own cache for modification. These operations are performed without the need for a Kill request and without having to perform retries of a losing ownership request.