Bus Agent Target Ready Signal Timing for Contiguous Writes
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Solution Overview
Problem
The inefficient utilization of processor bus bandwidth during combined writes in microprocessor architectures due to the Target Readiness Protocol (TRP) rules, which restrict the deassertion of the target ready signal (TRDY) until the data busy signal (DBSY) is deasserted, limiting the flow of data to memory.
Innovation Solution
A method and apparatus that decouples the relationship between DBSY and TRDY by allowing TRDY to be asserted as a one-cycle pulse early in the data transfer phase, enabling contiguous writes by asserting response signals and data busy signals accordingly, allowing for back-to-back write transactions without waiting for DBSY deassertion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the target ready signal (TRDY) is held until DBSY is deasserted according to conventional TRP rules, then signal synchronization is maintained, but bus bandwidth utilization deteriorates to only 67%
Solution Approach 1:
The patent applies preliminary action by asserting TRDY one clock cycle before the conventional time (during the first clock cycle of the data transfer phase rather than waiting until DBSY deassertion). This allows the bus agent to prepare for the next write transaction in advance, enabling contiguous writes and achieving 100% bus saturation without violating signal synchronization requirements.
2Productivity
If TRDY is deasserted early to enable contiguous writes, then bus saturation improves to 100%, but the handshake protocol between DBSY and TRDY deteriorates
Solution Approach 1:
The patent segments the TRDY signal assertion into distinct phases: it is asserted early during the data transfer phase to enable pipeline overlap, but maintained through the response phase to ensure proper handshake completion. This segmentation allows the system to achieve both early preparation for contiguous writes and reliable protocol completion.
3Productivity
If the handshake protocol between DBSY and TRDY is maintained strictly, then signal reliability is preserved, but data flow to memory deteriorates and bus saturation is limited
Solution Approach 1:
The patent implements continuity of useful action by ensuring TRDY remains asserted throughout the entire response phase even after early assertion. This continuous assertion allows the bus agent to continuously prepare for and execute contiguous write transactions without interruption, maintaining both high data flow rate and simplified signal coordination.
Data Source
AI summary
A method of performing contiguous write transactions on a processor bus according to an embodiment of the present invention includes detecting, by a bus agent, a request for a write cycle, asserting, by the bus agent, a target ready signal for one clock cycle in response to the write cycle during a first clock cycle of a data transfer phase of a prior write cycle or during a second clock cycle of a data transfer phase of a prior read cycle, asserting, by the bus agent, response signals in a next clock cycle following the clock cycle in which the target ready signal is asserted, asserting, by a processor, a data busy signal for the write cycle in the next clock cycle following the clock cycle in which the response signals are asserted, and asserting, by the processor, data for the write cycle when the data busy signal is asserted.