Bus Arbiter Power Mode Priority Scheduling

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Solution Overview

Problem

Conventional bus arbitration schemes in shared memory systems do not account for the power mode of memory channels, leading to increased power consumption and degraded system performance, as they do not differentiate between active and powered-down channels when granting access, often waking up memory channels unnecessarily.

Innovation Solution

The proposed solution involves dividing the shared memory into channels, determining their power modes, and assigning priorities to requests based on these modes, thereby scheduling access to maintain memory channels in a powered-down state for longer durations and prioritize active channels, using clock gating mechanisms and power mode tracking to minimize power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If conventional bus arbitration schemes are used to schedule memory access requests, then system simplicity is maintained, but power consumption increases due to unnecessary wake-up of memory channels

Engineering Contradiction:
Improvepower consumptionVSAvoidarbitration scheme complexity
Core Design Contradiction:
Use of energy by stationary objectVSDevice complexity

Solution Approach 1:

The arbitration scheme dynamically adjusts its behavior based on the power mode of memory channels. The bus arbiter receives power mode information and modifies request prioritization and scheduling decisions accordingly, transitioning from a static arbitration policy to a dynamic one that adapts to channel power states to reduce unnecessary wake-ups.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system implements feedback by having memory channels or memory controllers communicate their power mode status back to the bus arbiter. This feedback loop enables the arbiter to make informed scheduling decisions that consider the current power state of channels, allowing it to prioritize requests that would keep channels powered down longer.

Inventive Principle:
Principle #23Feedback

2Use of energy by stationary object

If memory channels are kept powered down longer to reduce power consumption, then power usage decreases, but access latency increases for requests requiring immediate service

Engineering Contradiction:
Improvepower consumptionVSAvoidaccess latency
Core Design Contradiction:
Use of energy by stationary objectVSLoss of time

Solution Approach 1:

The arbitration scheme dynamically adjusts prioritization based on channel power modes and request characteristics. When a channel is powered down, the system dynamically prioritizes requests from bus masters with strict latency requirements over those that can wait, enabling the arbiter to balance power savings with latency needs in real-time.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the prioritization parameter of memory access requests based on the power mode of destination channels. Requests to powered-down channels receive adjusted priorities compared to requests to active channels, allowing the system to optimize the trade-off between keeping channels powered down and meeting latency requirements.

Inventive Principle:
Principle #35Parameter changes

3Use of energy by stationary object

If power mode information is tracked and used in arbitration decisions, then power consumption is optimized, but system complexity increases due to additional tracking and decision logic

Engineering Contradiction:
Improvepower consumptionVSAvoidpower mode tracking complexity
Core Design Contradiction:
Use of energy by stationary objectVSDevice complexity

Solution Approach 1:

The bus arbiter's power mode tracking functionality is integrated into its existing request scheduling and prioritization logic. Rather than adding a separate complex tracking system, the arbiter utilizes its existing structural elements to handle power mode information, making the tracking mechanism more efficient and less complex.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9842068B2Methods of bus arbitration for low power memory access
Publication Date: 2017.12.12 QUALCOMM INC
  • US9842068B2 patent drawing
  • US9842068B2 patent drawing
  • US9842068B2 patent drawing

AI summary

Systems and method for arbitrating requests to a shared memory system for reducing power consumption of memory accesses, comprises determining power modes associated with memory channels of the shared memory system, assigning priorities to the requests based at least in part on the power modes, and scheduling the requests based on the assigned priorities. Latency characteristics and page hit rate are also considered for assigning the priorities.