Bus Arbiter Segmentation for Continuous Firmware Updates
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Solution Overview
Problem
Conventional navigation devices must cease all firmware operations and reboot to update firmware in flash memory, disrupting navigation functions during the process.
Innovation Solution
A mouse chip with additional hardware that allows direct generation and caching of function return values, enabling continuous navigation function operation during firmware updates by using separate buses for reading and writing firmware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If firmware in flash memory is updated using conventional methods, then firmware can be updated, but all firmware operations must cease and the system must be rebooted, disrupting navigation functions
Solution Approach 1:
The patent divides the single bus into two separate buses: a first bus for reading function return values and a second bus for updating firmware. This segmentation allows simultaneous firmware updates and navigation operations without mutual interference, resolving the contradiction between update capability and operational continuity.
Solution Approach 2:
The patent introduces a cache memory as an intermediary between the flash memory and the processing unit. The cache stores function return values that can be retrieved via the first bus even while firmware is being updated through the second bus, enabling continuous navigation operations during firmware updates.
2Device complexity
If a single bus is used for both reading function return values and updating firmware, then device complexity is reduced, but firmware updates interrupt ongoing operations
Solution Approach 1:
The patent segments the single bus into two independent buses (first bus for reading, second bus for writing), allowing simultaneous operations without interference. This resolves the contradiction by accepting increased structural complexity in exchange for operational continuity during firmware updates.
Solution Approach 2:
The patent adds a temporal dimension to bus operations by enabling concurrent reading and writing operations on different buses simultaneously. This dimensional expansion allows firmware updates and navigation operations to proceed in parallel, resolving the interruption problem.
3Stability of the object's composition
If flash memory is accessed serially for firmware updates, then flash memory structure is maintained, but random access capability required for navigation functions is lost
Solution Approach 1:
The cache memory acts as an intermediary that provides random access capability for navigation functions while the flash memory maintains its serial access structure for firmware updates. The cache bridges the gap between serial flash storage and random access requirements, resolving the contradiction between structural stability and access speed.
Solution Approach 2:
The patent segments the memory access paths by introducing separate buses: the first bus provides fast random access to cached function return values for navigation operations, while the second bus handles serial firmware updates. This segmentation allows both serial flash structure and fast random access to coexist.
Data Source
AI summary
There is provided a control chip including a microcontroller unit (MCU), a bus arbiter, a first bus, a second bus, a void hardware, a cache controller, a flash controller and a flash memory, wherein the flash memory is recorded with a firmware. When the MCU does not receive an update instruction, the bus arbiter reads, according to a function command of the MCU, a function return value associated with the function command from the flash memory via the first bus, the cache controller and the flash controller. When the MCU receives the update instruction, the bus arbiter updates the firmware in the flash memory via the second bus and the flash controller, and the void hardware actively replies a void return value associated with the function command to the MCU to replace the function return value.