Bus Arbiter Bandwidth Control for Semiconductor Storage
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Solution Overview
Problem
The bandwidth of the bus in semiconductor storage devices acts as a bottleneck, leading to slowed data transfer rates and prolonged access times, which degrades the performance of nonvolatile memory chips during data transfer operations.
Innovation Solution
A bus arbiter dynamically controls the use of the bus by implementing a use notice mechanism, where nonvolatile memory interfaces notify the coordination circuit of intended data transfers, and the bus arbiter ensures that the number of bus masters using the bus does not exceed an upper limit, preventing bandwidth bottlenecks and optimizing data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple nonvolatile memory chips transfer data in parallel via the bus, then data transfer capacity increases, but the bus bandwidth becomes a bottleneck causing transfer rate to slow down
Solution Approach 1:
The bus arbiter dynamically adjusts the number of allowed bus masters based on current bus utilization and bandwidth conditions. The arbitration mechanism changes operational parameters in real-time, allowing the system to adapt between high-throughput mode (when bus is underutilized) and rate-limited mode (when bus bandwidth is approaching capacity), thus resolving the contradiction between transfer capacity and transfer rate
Solution Approach 2:
The bus arbitration system implements feedback control by monitoring bus utilization metrics and adjusting the number of permitted simultaneous bus masters accordingly. When the bus approaches bandwidth saturation, the arbiter reduces the number of active bus masters, preventing performance degradation. This closed-loop control ensures optimal balance between parallel transfer capacity and maintained transfer rate
2Productivity
If the number of bus masters using the bus is increased, then data transfer parallelism improves, but access performance degrades due to bandwidth constraints
Solution Approach 1:
The system dynamically controls the number of bus masters based on real-time bus conditions. When bus bandwidth is available, more masters are permitted to operate in parallel, maximizing throughput. When bandwidth constraints are detected, the arbiter reduces the number of active masters, preventing access time degradation. This dynamic adjustment optimizes the balance between parallelism and access performance
Solution Approach 2:
The bus arbiter performs preliminary arbitration before granting bus access, evaluating current bus utilization and predicting potential bandwidth saturation. By proactively limiting the number of bus masters before congestion occurs, the system prevents access time degradation while maintaining optimal parallelism, rather than reacting after performance degradation has already occurred
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes a volatile memory, nonvolatile memory chips, channels, nonvolatile memory interfaces, and a bus arbiter. Each of the channels is connected to at least one nonvolatile memory chip of the nonvolatile memory chips. Each of the nonvolatile memory interfaces is connected to at least one channel of the channels and controls the at least one nonvolatile memory chip via the connected channel. The bus arbiter controls use of a bus in data transfer between the volatile memory and each of the nonvolatile memory chips in accordance with a bandwidth of the bus.