Bus Arbiter Successive Transaction Grouping for Memory Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In bus arbitration systems, simultaneous requests from multiple master devices can lead to non-successive transaction transfers to slave devices, reducing data processing speed and page hit rates, especially for memory devices, thereby impacting overall system performance.
Innovation Solution
A bus arbiter that groups transactions based on successive request signals from master devices, generating an arbitration stop signal to determine whether to perform arbitration operations, ensuring that successive transactions are transferred continuously to the slave device, maintaining access patterns and improving memory access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bus arbitration is performed to manage simultaneous requests from multiple master devices, then access control and fairness are improved, but transaction succession and data processing speed deteriorate
Solution Approach 1:
The bus arbiter dynamically adjusts its arbitration behavior based on the request type. For successive requests (same memory page), it suppresses arbitration to maintain transaction succession. For non-successive requests (different memory pages), it performs arbitration to ensure fair access control. This dynamic adaptation resolves the contradiction between access control and data processing speed.
Solution Approach 2:
The arbitration mechanism is applied selectively to different types of transactions. Successive transactions (local memory access pattern) bypass arbitration to maintain continuity, while non-successive transactions (cross-page access) undergo full arbitration. This local differentiation allows the system to optimize for both access control fairness and processing speed in different contexts.
2Reliability
If arbitration is performed on every transaction request, then fairness among master devices is improved, but transaction succession and page hit rate deteriorate
Solution Approach 1:
Instead of performing full arbitration on every transaction, the system applies partial arbitration only when necessary. When a master device sends successive requests for the same memory page, the arbiter suppresses arbitration actions that would interrupt the succession. Arbitration is only fully applied when master devices are competing for different memory pages. This partial application of arbitration maintains fairness where needed while preserving page hit rate where succession is possible.
3Reliability
If successive transactions are not grouped, then arbitration fairness is maintained, but data processing speed and system performance deteriorate
Solution Approach 1:
The bus arbiter dynamically adapts its behavior based on the transaction pattern. When successive requests are detected (same memory page), it dynamically suppresses arbitration to group transactions and maintain data processing speed. When different memory pages are accessed, it dynamically resumes arbitration to maintain fairness. This dynamic adaptation allows the system to optimize for speed during succession while preserving fairness during competition.
Data Source
AI summary
A bus arbiter includes an arbitration stop determining unit and a transaction arbitrating unit. The arbitration stop determining unit generates an arbitration stop signal based upon transaction grouping request signals which indicate whether successive transactions are requested. The transaction arbitrating unit selectively performs an arbitration operation based upon the arbitration stop signal.