Bus Arbitration Mechanism for Master Devices

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Solution Overview

Problem

Existing bus arbitration methods in computer systems require a bus arbitrator and lack design flexibility, necessitating adjustments in time sequence, priority, and other parameters when the number of master or slave devices changes.

Innovation Solution

A bus arbitration mechanism where master devices detect each other's presence and adjust their participation in bus arbitrations based on successful or unsuccessful access to a slave device, allowing equal access rights without a bus arbitrator, with successful access devices opting out of subsequent arbitrations and unsuccessful devices continuing to attempt access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a bus arbitrator is used to manage master devices accessing slave devices, then bus arbitration can be performed in an organized manner, but the device complexity increases and design flexibility is reduced

Engineering Contradiction:
Improvebus arbitration organizationVSAvoidbus arbitrator requirement
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent removes the bus arbitrator component from the system entirely. Instead of having a dedicated arbitration device, each master device independently performs arbitration by detecting bus states and timing their access attempts, thereby extracting the arbitration function from a separate component and distributing it across all master devices.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Each master device serves itself by autonomously determining when to access the bus based on detecting the number of operating master devices and the current bus state. The system uses self-service arbitration where devices monitor bus conditions and autonomously decide their access timing without external arbitration control.

Inventive Principle:
Principle #25Self-service

2Adaptability or versatility

If the number of master devices or slave devices changes, then the system needs to adapt to new configurations, but time sequence and priority parameters must be adjusted again, extending the development schedule

Engineering Contradiction:
Improveconfiguration adaptabilityVSAvoiddevelopment schedule extension
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent implements dynamic adaptation where each master device determines the current number of operating master devices through bus detection and automatically adjusts its arbitration behavior accordingly. This dynamic approach eliminates the need for static reconfiguration when device counts change, as the system naturally adapts to the current configuration through real-time detection and adjustment of arbitration timing.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If master devices access slave devices without a bus arbitrator, then design flexibility improves and development schedule is shortened, but ensuring equal access rights for all master devices becomes more difficult

Engineering Contradiction:
Improvedesign flexibilityVSAvoidequal access rights guarantee
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent creates equipotential access conditions by having all master devices use the same arbitration methodology - detecting the total number of operating master devices and using identical timing logic based on that detected count. This ensures that under equal conditions (same detected device count), all master devices have equal probability and opportunity to access the bus, maintaining fairness without requiring a central arbitrator.

Inventive Principle:
Principle #12Equipotentiality

Data Source

PatentUS10581973B2Computer system and bus arbitration method
Publication Date: 2020.03.03 WIWYNN CORP
  • US10581973B2 patent drawing
  • US10581973B2 patent drawing

AI summary

A computer system and a bus arbitration method are provided. The computer system includes a bus, a plurality of master devices, and a slave device. The master devices and the slave device are coupled to the bus. Each of the master devices determines the number of the operating master devices through the bus. When a first master device intends to access the slave device, the first master device performs a bus arbitration on the slave device and attempts to access the slave device. If the slave device is accessed successfully, the first master device does not participate in N number of times of subsequent bus arbitrations. If the slave device is accessed unsuccessfully, the first master device determines whether the slave device is released. If the slave device is released, the first master device performs a next bus arbitration and attempts to access the slave device continuously.