Bus Arbitration System with Port-Level Segmentation
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Solution Overview
Problem
Current bus systems in integrated circuits, such as AHB and AXI, allow only one master device to have active access to the bus at a time, leading to inefficiencies in data transfer due to overlapping data message management limitations.
Innovation Solution
Implementing a bus arbitration system with individual port arbiters for each peripheral, allowing multiple master devices to access the bus simultaneously by using a request splitter to direct connection requests based on port identifiers to the corresponding port arbiters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single bus arbiter is used to manage access to peripherals, then device complexity is reduced, but bus utilization efficiency deteriorates due to inability to handle overlapping data messages from multiple masters simultaneously
Solution Approach 1:
The single bus arbiter is segmented into multiple port arbiters, each responsible for a specific peripheral port. This segmentation allows simultaneous arbitration for multiple ports, enabling overlapping data messages from different masters to be handled in parallel, thus improving bus utilization efficiency without proportionally increasing overall system complexity.
Solution Approach 2:
The arbitration system transitions from a single-dimension sequential arbitration model to a multi-dimension parallel arbitration model by introducing port identifiers and distributing arbiters across different port dimensions. This allows the system to process multiple arbitration requests simultaneously across different port dimensions, resolving the contradiction between efficiency and complexity.
2Productivity
If only one master device is allowed to access the bus at a time, then data message overlap is avoided, but data transfer efficiency deteriorates due to idle bus periods when multiple masters have data to transfer
Solution Approach 1:
The bus arbitration functionality is segmented into multiple independent port arbiters, each capable of independently managing access for its associated peripheral. This allows multiple masters to simultaneously access different peripherals without data message overlap, as each port arbiter ensures proper sequencing for its specific port while enabling parallel operations across ports.
Solution Approach 2:
Port identifiers act as intermediaries that route connection requests from masters to the appropriate port arbiters. This intermediary mechanism enables the system to distinguish between different target peripherals and direct traffic accordingly, allowing simultaneous data transfers to different ports while maintaining data message integrity through proper routing.
3Productivity
If a single arbiter manages all peripheral access, then the arbitration logic is simplified, but bottlenecks occur when multiple masters simultaneously request access to different peripherals
Solution Approach 1:
The centralized arbitration logic is segmented into distributed port arbiters, with each arbiter handling a specific peripheral port. This segmentation eliminates the bottleneck at the single arbiter by distributing the arbitration workload across multiple independent units, thereby increasing overall arbitration throughput while maintaining relatively simple individual arbiter designs.
Solution Approach 2:
Each port arbiter independently manages its own port's access requests without requiring intervention from a central arbitration authority. This self-service capability allows port arbiters to autonomously handle connection requests for their respective peripherals, increasing arbitration throughput through parallel autonomous decision-making while keeping each arbiter's internal logic simple.
Data Source
AI summary
A bus arbitration system, a method of connecting a master device and a peripheral over a bus system of an IC and an IC is provided. In one embodiment, the bus arbitration system includes: (1) a bus system configured to couple master devices to peripherals, port arbiters coupled to the bus system, wherein each of the port arbiters uniquely corresponds to one of the peripherals and is configured to manage access to the uniquely corresponding peripheral and a request splitter configured to receive connection requests from the master devices for the peripherals and direct the connection requests to a specific one of the port arbiters according to a port identifier associated with each of the connection requests.