Bus Arbitration Routing Failover Mechanism

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Solution Overview

Problem

Existing failover mechanisms in computer systems are limited in addressing failures of bus components and link/path connections, particularly in RAID systems and fibre channel loops, and do not provide comprehensive redundancy across all failure scenarios.

Innovation Solution

A bus routing and failover mechanism that utilizes a system architecture with multiple bus masters and arbiters, where arbiters monitor bus health and manage failover and routing, enabling data, control, and command signal migration across a distributed network of bus masters and slave devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single bus and arbiter architecture is used, then device complexity is reduced, but reliability deteriorates due to single point of failure

Engineering Contradiction:
Improvesystem availabilityVSAvoidbus architecture complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system divides the bus architecture into multiple independent bus segments (first bus, second bus) with separate arbiters (first arbiter, second arbiter). Each bus-master device can be associated with multiple buses, creating redundant pathways. This segmentation eliminates single points of failure while maintaining manageable complexity through modular organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system pre-establishes alternative bus pathways and arbiter assignments before failures occur. When a bus or arbiter fails, the system has already configured backup routes through which bus-master devices can switch to alternative buses and arbiters, enabling rapid failover without complex real-time decision-making.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If redundant bus paths are implemented, then reliability improves through failover capability, but device complexity increases due to multiple arbitration mechanisms

Engineering Contradiction:
Improvefault toleranceVSAvoidarbitration system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Each arbiter is designed with multi-functionality to handle multiple bus-master devices across different buses. The arbiters can service requests from any associated bus-master on any associated bus, reducing the need for dedicated arbitration pairs and simplifying the overall arbitration system while maintaining redundant pathways.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system introduces bus-association data structures as intermediaries that manage the relationships between bus-master devices, buses, and arbiters. These data structures act as mediators that coordinate failover operations and route selection, reducing the complexity of direct arbiter-to-arbiter communication and coordination.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If bus-master devices are connected to multiple buses, then availability improves through alternative paths, but difficulty of detecting and measuring failures increases

Engineering Contradiction:
Improvecontinuous operation capabilityVSAvoidfailure detection complexity
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The system implements feedback mechanisms where bus-master devices monitor the status of their associated buses and arbiters. When a failure is detected on one bus, the bus-master receives feedback about the failure state and automatically switches to an alternative bus through the bus-association data structures. This feedback loop simplifies failure detection by distributing monitoring responsibilities across active components.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9916213B1Bus arbitration with routing and failover mechanism
Publication Date: 2018.03.13 BITMICRO LLC
  • US9916213B1 patent drawing
  • US9916213B1 patent drawing
  • US9916213B1 patent drawing

AI summary

In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.