Bus Arbitration Routing Failover Mechanism
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Solution Overview
Problem
Existing failover mechanisms in computer systems are limited in addressing failures of links or paths between controller components and storage devices, particularly in non-fibre channel arbitrated loop architectures, and do not provide comprehensive redundancy for all potential failures.
Innovation Solution
A bus routing and failover mechanism that utilizes a system architecture with multiple bus masters and arbiters, where arbiters monitor bus health, generate status signals, and employ an arbiter priority selector to reroute data and control signals across a distributed network of bus masters and slave devices, ensuring fault-tolerant and load-balanced data distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single-controller architecture is used, then the system structure is simple, but the system reliability is low when link failures occur
Solution Approach 1:
The system is segmented into multiple independent controllers (primary and secondary) that can operate autonomously. Each controller manages specific bus masters and slave devices, allowing the system to partition functionality and maintain operation even when one segment fails.
Solution Approach 2:
The system dynamically changes operational parameters by switching controller roles. When a link failure is detected, the secondary controller transitions from standby to active status, changing the system's operational state from single-controller to failover mode with the surviving controller assuming full responsibility.
2Reliability
If redundant controller components are added for failover, then system reliability improves, but device complexity increases
Solution Approach 1:
The secondary controller is pre-configured with all necessary control logic and data structures before failure occurs. Status registers and control registers are pre-established, allowing immediate takeover without complex real-time configuration during failover events.
Solution Approach 2:
Status registers and control registers serve as intermediaries between controllers and bus masters/slave devices. These registers standardize the interface, allowing the secondary controller to assume control by simply taking over the same register set without requiring complex adaptation logic.
3Reliability
If comprehensive link failure detection is implemented, then system robustness improves, but the complexity of detecting and measuring failures increases
Solution Approach 1:
The system implements continuous feedback monitoring through status registers that track link health. The secondary controller monitors the primary controller's status registers, and bus masters monitor link status, creating multiple feedback loops that automatically detect failures without complex diagnostic procedures.
Solution Approach 2:
The status registers automatically update themselves based on link conditions, and the secondary controller automatically detects failures by monitoring these self-updating registers. The system performs self-diagnosis without requiring external intervention or complex measurement instruments.
Data Source
AI summary
In an embodiment of the invention, an apparatus comprises: a plurality of bus masters and a plurality of bus arbiters to support routing and failover, wherein each bus arbiter is coupled to a plurality of bus masters; and a central processing unit (CPU) coupled to at least one of the bus arbiters; wherein the CPU is configured to execute a firmware that chooses bus re-routing or failover in response to a bus failure. In another embodiment of the invention, a method comprises: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions that permit a method comprising: choosing, by a central processing unit (CPU) coupled to a plurality of bus arbiters, bus re-routing or failover in response to a bus failure.