Bus Arbitration Switching Circuit for SoC Memory Access
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Solution Overview
Problem
Conventional bus arbitration switching circuits in SoC systems face delays that hinder high-speed memory access, particularly when the number of function modules exceeds 16, making it difficult to maintain a switching delay within 8 ns at clock frequencies above 125 MHz.
Innovation Solution
A method and system that compare priorities of function modules using a binary code to determine the location of the module with the highest priority, performing logic operations on location and bus information to switch the bus to the highest-priority module, reducing the delay by using a comparator of the first degree, an AND-gate of the Nth degree, and an OR-gate of the Nth degree.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a tree comparator is used to compare priorities of function modules, then the arbitration switching circuit can determine the highest priority module, but the delay increases significantly when the number of function modules exceeds 16
Solution Approach 1:
The patent segments the priority comparison process into two independent parts: a counter that generates comparison results for all function modules simultaneously, and a comparator that selects the highest priority module. This segmentation allows parallel processing of comparison operations, reducing the delay from logarithmic (tree comparator) to linear time complexity.
Solution Approach 2:
The counter performs preliminary comparison of all function module priorities simultaneously and generates intermediate comparison results before the final selection. This preliminary action distributes the comparison workload across multiple parallel operations, reducing the critical path delay while maintaining accurate priority determination.
2Adaptability or versatility
If the number of function modules increases to support more parallel operations, then the system functionality improves, but the arbitration switching delay exceeds 8 ns at clock frequencies above 125 MHz
Solution Approach 1:
The patent divides the arbitration function into a counter module that processes all function modules in parallel and a comparator module that performs final selection. This segmentation enables the system to scale with the number of function modules while maintaining sub-8ns delay at high clock frequencies by distributing the computational burden across parallel operations.
Solution Approach 2:
The patent changes the operational parameters of the arbitration circuit by using a counter-based approach instead of a tree comparator. This parameter change transforms the time complexity from O(log N) to O(N) parallel operations, allowing the circuit to maintain fast switching speeds even as the number of function modules increases to support more parallel operations.
3Measurement precision
If a multi-selector is used to switch buses based on priority, then the correct function module can be selected, but the circuit complexity and delay increase
Solution Approach 1:
The patent segments the selection function into a counter that generates location information for the highest priority module and a simple comparator that uses this information to control bus switching. This segmentation replaces the complex multi-selector with a simpler architecture that achieves the same selection function with reduced complexity and delay.
Solution Approach 2:
The patent introduces location information as an intermediary signal that carries the selection result from the counter to the comparator and bus switching circuit. This intermediary simplifies the overall architecture by decoupling the priority comparison function from the bus switching function, reducing circuit complexity while maintaining accurate module selection.
Data Source
AI summary
Method, system, bus arbitration device for accessing a memory are described. According to one embodiment, priorities of N function modules accessing the memory are compared to obtain location information of a function module with the highest priority. A bus of the function modules accessing the memory is switched to the function module with the highest priority by performing logic operation on the location information and bus information of each function module. Further, a bus arbitration device including a priority arbitration unit and a bus switching unit is described.