Bus Architecture Redundancy Comparator Power Reduction
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Solution Overview
Problem
Current bus architectures for memory devices consume high power due to unnecessary comparison of all bits, even when only a few bits match, leading to increased power consumption as the number of redundancy resources and page size increase.
Innovation Solution
The proposed bus architecture compares only the most significant bits first, generating an enable signal to enable the comparison of less significant bits only when the former match, thereby reducing power consumption by limiting switching activity to necessary periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all bits of the address signal are compared with the redundancy address during the column counting phase, then the comparison function is complete and reliable, but the power consumption increases significantly
Solution Approach 1:
The address signal bits are divided into two groups: most significant bits (MSBs) and less significant bits (LSBs). The comparison operation is segmented into two phases: first comparing MSBs, then conditionally comparing LSBs based on the MSB match result. This segmentation allows the system to perform only necessary comparisons, reducing power consumption while maintaining comparison reliability.
Solution Approach 2:
Instead of performing the complete comparison of all address bits in every case, the system performs a partial comparison of only the MSBs first. The LSB comparison is performed only when necessary (when MSBs match). This partial action approach eliminates unnecessary full comparisons, directly reducing power consumption during the column counting phase.
2Loss of time
If the comparison of all address bits is performed continuously, then the comparison result is always available, but the switching activity and current consumption increase
Solution Approach 1:
The comparison operation is structured as a periodic two-phase process: first phase compares MSBs, second phase conditionally compares LSBs. This periodic structure with conditional execution allows the system to maintain comparison functionality while reducing average switching activity and current consumption by skipping the LSB comparison phase when MSBs do not match.
3Adaptability or versatility
If the number of redundancy resources and page size increase, then the memory capacity and functionality are improved, but the power consumption during comparison operations increases
Solution Approach 1:
The comparison architecture is segmented into hierarchical levels with MSB comparison serving as a filter before LSB comparison. This segmentation becomes increasingly beneficial as the number of redundancy resources and page size increase, because the MSB comparison quickly eliminates non-matching entries, preventing unnecessary power consumption in the LSB comparison stage for large memory configurations.
Data Source
AI summary
Disclosed herein is a redundancy resource comparator for a bus architecture of a memory device for comparing an address signal being received from an address signal bus and a redundancy address being stored in a latch of the memory device. Disclosed is also a corresponding bus architecture and comparison method.