Bus Attachment Device for Directed Interrupt Virtualization

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Solution Overview

Problem

In multiprocessor computer systems, efficiently routing interrupts generated by bus-connected modules to the appropriate processor is challenging, especially when communicating with a guest operating system on a virtual machine, as the mapping between logical and virtual processor IDs is dynamic and not static, leading to inefficiencies in interrupt signal handling.

Innovation Solution

A computer program product that enables direct targeting of interrupt signals to specific processors using a bus attachment device, which translates interrupt target IDs to logical processor IDs and checks for current assignments, allowing for efficient handling by the most suitable processor and providing a fallback broadcast mechanism to ensure interrupts reach the correct target even with dynamic mapping changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If broadcasting is used to forward interrupt signals to multiple processors, then the interrupt signal can reach the correct target processor despite dynamic mapping changes, but the interrupt handling efficiency deteriorates due to successive forwarding and low probability of immediate suitable processor availability

Engineering Contradiction:

Improveinterrupt delivery reliabilityVSAvoidinterrupt handling efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The bus attachment device performs preliminary translation of the interrupt target ID to a logical processor ID before forwarding the interrupt signal. This advance translation enables direct routing to the target processor without requiring successive broadcasting and waiting for processor availability, thus improving both efficiency and reliability

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The bus attachment device acts as an intermediary between the interrupt source and the processor. It translates the virtual processor ID to a logical processor ID and forwards the interrupt signal directly to the appropriate processor, eliminating the need for broadcasting and successive forwarding while ensuring reliable delivery

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If direct targeting of interrupt signals to specific processors is implemented, then interrupt handling efficiency improves by directly addressing the target processor, but the system complexity increases due to dynamic mapping management

Engineering Contradiction:

Improveinterrupt handling efficiencyVSAvoidmapping management complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The bus attachment device automatically performs the translation of interrupt target IDs to logical processor IDs using its internal translation logic. This self-service approach eliminates the need for external management of dynamic mappings, reducing system complexity while maintaining direct targeting efficiency

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The translation and mapping management functions are extracted from the general system and concentrated in the bus attachment device. This isolation of complexity to a single component simplifies the overall system architecture while enabling efficient direct interrupt routing

Inventive Principle:

Principle #2Taking out (Extraction)

3Adaptability or versatility

If the hypervisor dynamically changes processor mappings while the guest operating system is running, then system adaptability improves, but interrupt routing accuracy deteriorates due to mismatches between virtual and logical processor IDs

Engineering Contradiction:

Improveprocessor assignment flexibilityVSAvoidinterrupt target accuracy

Core Design Contradiction:

Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The bus attachment device performs preliminary translation of the virtual processor ID to the current logical processor ID before the interrupt signal is forwarded. This advance translation ensures that even if mappings change dynamically, the interrupt signal is routed to the correct current target processor, maintaining accuracy while allowing flexibility

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system uses the interrupt target ID as feedback to determine the current logical processor ID through translation. This feedback mechanism ensures that dynamic mapping changes are automatically accounted for, maintaining accurate interrupt routing despite hypervisor-induced reassignments

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS11829790B2Directed interrupt virtualization with fallback

Publication Date: 2023.11.28 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A processor receives an interrupt signal. The interrupt signal is received with an interrupt target ID identifying a target processor for handling the interrupt signal. The processor is a target of the interrupt signal directly. A check is made as to whether the processor is the target processor identified by the interrupt target ID. The checking includes performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor. Based on the checking being successful, the interrupt signal is accepted for handling by the processor.