Bus Bandwidth Smoothing via Dynamic Frame Data Intervals
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Solution Overview
Problem
In imaging systems, the common bus arbitration can lead to bus ownership stagnation for low-priority functional blocks due to continuous DMA transfer requests from high-priority blocks, causing interference between frame data transfers and impacting processing efficiency.
Innovation Solution
A data transfer device with a buffer unit, write control unit, read control unit, interface unit, and band-smoothing unit that temporarily stores and manages transfer data, adjusts read/write intervals based on data position within a frame image, and adjusts time intervals to prevent data interference between frames.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-priority functional block continuously outputs DMA transfer requests to maintain high data transfer speed, then the data transfer speed is improved, but bus ownership does not pass to other functional blocks causing processing stagnation
Solution Approach 1:
The patent applies periodic action by controlling the high-priority functional block to output DMA transfer requests at regular time intervals rather than continuously. This periodic transmission pattern allows the bus arbiter to allocate bus ownership to other functional blocks between transfer requests, ensuring that while maintaining high data transfer speed, other processes do not stagnate and the system achieves balanced overall productivity.
2Productivity
If the common bus bandwidth is smoothed by outputting DMA transfer requests at regular time intervals, then bus arbitration fairness is improved, but transfer data of certain frames may interfere with transfer data of next frames
Solution Approach 1:
The patent applies segmentation by dividing the frame image data into multiple regions (first region, second region, third region) with different data densities. By identifying and separately handling the final transfer data of each region, the system can apply different time interval controls: longer intervals for regular data to ensure bus fairness, and shorter intervals for final frame data to prevent inter-frame interference, thus maintaining both arbitration fairness and data integrity.
Solution Approach 2:
The patent applies dynamics by dynamically adjusting the time interval between DMA transfer requests based on the data position within the frame. The band-smoothing unit switches between first time intervals (for non-final data) and second time intervals (for final frame data), making the transmission timing adaptive rather than fixed. This dynamic adjustment allows the system to optimize for bus fairness during regular transmission while preventing data interference at critical frame boundaries.
3Device complexity
If a fixed time interval is used for all transfer data to simplify control, then device complexity is reduced, but data interference between frames occurs and processing efficiency decreases
Solution Approach 1:
The patent applies preliminary action by having the band-smoothing unit determine in advance whether the current transfer data is the final data of a frame before initiating the transfer. Based on this preliminary determination, the system pre-selects the appropriate time interval (first or second), avoiding the need for complex real-time adjustments during transfer and simplifying control while ensuring data integrity through appropriate interval selection.
Data Source
AI summary
A data transfer device including a buffer unit configured to temporarily store transfer data that is transferred to a common bus, a write control unit configured to write input data as the transfer data to the buffer unit, a read control unit configured to read the transfer data from the buffer unit, an interface unit configured to transfer the transfer data to the common bus according to a predetermined bus protocol, the transfer data being read from the buffer unit by the read control unit, and a band-smoothing unit configured to smooth a band of the common bus by switching between the time intervals between pieces of the transfer data based on a position of the transfer data in a frame image, during a period when the transfer data is transferred to the common bus based on a position of the transfer data in a frame image.