Bus-Based Programmable Interconnect for IC Clock Skew
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Solution Overview
Problem
Designing reliable clock networks for large programmable integrated circuits (ICs) is challenging due to clock skew issues, which require significant engineering resources and can impact the design cycle, and the extensive global clock networks consume substantial power.
Innovation Solution
The integration of bus-based programmable interconnect structures with handshake logic and asynchronous routing, including C-elements and multiplexers, to manage data and control signals efficiently, reducing the need for global clock networks and addressing clock skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extensive dedicated clock networks with clock management blocks are used to provide clock signals to all portions of the IC, then clock distribution coverage is improved, but power consumption increases and device complexity increases
Solution Approach 1:
The patent removes the extensive dedicated global clock network and clock management blocks from the IC architecture. Instead of having a separate clock distribution system, the invention uses asynchronous routing with handshake logic and C-elements to manage timing and coordination between logic blocks, thereby eliminating the power consumption and complexity associated with traditional global clock networks while maintaining reliable signal distribution.
Solution Approach 2:
The patent replaces the mechanical/electrical clock signal distribution system with an asynchronous control mechanism based on handshake logic and C-elements. This substitution eliminates the need for synchronized clock signals and replaces it with event-driven communication, reducing power consumption and device complexity while maintaining system reliability.
2Reliability
If extensive dedicated clock networks with clock management blocks are used to provide clock signals to all portions of the IC, then clock distribution coverage is improved, but device complexity increases
Solution Approach 1:
The patent removes the extensive dedicated global clock network and clock management blocks from the IC architecture. Instead of having a separate clock distribution system, the invention uses asynchronous routing with handshake logic and C-elements to manage timing and coordination between logic blocks, thereby eliminating the power consumption and complexity associated with traditional global clock networks while maintaining reliable signal distribution.
Solution Approach 2:
The patent replaces the mechanical/electrical clock signal distribution system with an asynchronous control mechanism based on handshake logic and C-elements. This substitution eliminates the need for synchronized clock signals and replaces it with event-driven communication, reducing power consumption and device complexity while maintaining system reliability.
3Reliability
If traditional clock networks are used, then clock signal distribution is achieved, but design and testing time increases
Solution Approach 1:
The patent removes the extensive dedicated global clock network and clock management blocks from the IC architecture. Instead of having a separate clock distribution system, the invention uses asynchronous routing with handshake logic and C-elements to manage timing and coordination between logic blocks, thereby eliminating the power consumption and complexity associated with traditional global clock networks while maintaining reliable signal distribution.
Data Source
AI summary
Integrated circuits (ICs) having bus-based programmable interconnect structures are provided. An IC includes substantially similar logic blocks and a programmable interconnect structure programmably interconnecting the logic blocks. The programmable interconnect structure includes bus structures and programmable switching structures programmably interconnecting the bus structures. Each bus structure includes N data lines, where N is an integer greater than one, and N commonly controlled storage elements (e.g., latches) for storing data on the N data lines. In some embodiments, at least one of the bus structures includes handshake logic, including a C-element coupled to drive a ready line, to receive an acknowledge line, and to provide a control signal to each of the N storage elements in the bus structure. In some embodiments, each of the programmable switching structures includes N M-input data multiplexers, an M-input ready multiplexer, and an M-output acknowledge demultiplexer, M being an integer greater than one.