Bus Bridge Transaction Ordering via Counter Stalling

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Solution Overview

Problem

In complex Systems on Chips (SoCs), maintaining the order of transactions through a bus fabric is crucial to prevent stale data issues, but existing mechanisms fail to ensure this order when transactions are processed across different bus protocols with separate paths for read and write operations.

Innovation Solution

The implementation of control logic within a bridge that uses counters to track outstanding read and write transactions, stalling transactions if the opposite type is still in progress, ensures that read and write operations are completed in the correct order by utilizing separate paths for each type of transaction on the second bus protocol.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If separate connection paths are used for read and write transactions on the second bus, then transaction processing efficiency is improved, but transaction order may be violated

Engineering Contradiction:
Improvetransaction processing efficiencyVSAvoidtransaction order maintenance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The bridge control logic acts as an intermediary between the first bus (shared path) and the second bus (separate paths). It uses counters to track outstanding transactions and mediates the transition between buses, ensuring that read and write transactions maintain their relative order even though they traverse separate paths on the second bus.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The control logic performs preliminary actions by stalling transactions before they enter the second bus. When a read transaction is detected, the control logic stalls subsequent write transactions until the read transaction completes, ensuring proper ordering is established before transactions diverge onto separate paths.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If a single shared connection path is used for both read and write transactions on the first bus, then transaction order is maintained, but transaction processing efficiency decreases

Engineering Contradiction:
Improvetransaction order maintenanceVSAvoidtransaction processing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system segments the transaction paths at the bridge. The first bus maintains a shared path for simplicity and order maintenance, while the second bus is segmented into separate read and write paths for improved efficiency. The bridge control logic manages the transition between these different path configurations.

Inventive Principle:
Principle #1Segmentation

3Reliability

If transactions are stalled to maintain order, then transaction order is preserved, but processing time increases

Engineering Contradiction:
Improvetransaction order maintenanceVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The control logic uses feedback from transaction responses to manage stalling. When a read transaction completes and its response is received, the control logic uses this feedback to un-stall any waiting write transactions. This feedback mechanism ensures minimal unnecessary stalling while maintaining order.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9229896B2Systems and methods for maintaining an order of read and write transactions in a computing system
Publication Date: 2016.01.05 APPLE INC
  • US9229896B2 patent drawing
  • US9229896B2 patent drawing
  • US9229896B2 patent drawing

AI summary

Systems and methods for maintaining an order of read and write transactions for each source through a bridge in a bus fabric. The bridge provides a connection from a first bus to a second bus within the bus fabric. The first bus has a single path for read and write transactions and the second bus has separate paths for read and write transactions. The bridge maintains a pair of counters for each source in a SoC to track the numbers of outstanding read and write transactions. The bridge prevents a read transaction from being forwarded to the second bus if the corresponding write counter is non-zero, and the bridge prevents a write transaction from being forwarded to the second bus if the corresponding read counter is non-zero.