Bus Bridge Data Transfer Device with Segmented Buffers
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Solution Overview
Problem
Conventional bus bridges face challenges in optimizing data transfer performance between memory and I/O buses due to differing protocols, inability to handle out-of-order execution, and limited flexibility in coping with protocol changes, leading to inefficiencies and the need for frequent hardware replacements.
Innovation Solution
A data transfer device with separate buffers and a control information table that allows for the storage and processing of data as packets, enabling out-of-order execution and overtaking control, while accommodating different protocols by using a control section to manage data access and storage based on sequence IDs and storing position information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional bus bridges use shared transmission and reception buffers for both memory bus and I/O bus protocols, then device complexity is reduced, but data transfer performance cannot be optimized for different protocols and adaptability to protocol changes is limited
Solution Approach 1:
The patent segments the buffer system into four distinct buffers: transmission buffer for memory bus, reception buffer for memory bus, transmission buffer for I/O bus, and reception buffer for I/O bus. This segmentation allows each buffer to be optimized for its specific protocol while maintaining overall system adaptability to different bus protocols.
2Productivity
If conventional bus bridges process packets in strict order, then reliability of data transfer is improved, but productivity is reduced due to inability to perform out-of-order execution
Solution Approach 1:
The patent implements preliminary actions by storing incoming packets in buffers with associated sequence information before final delivery. The control section manages packet sequencing, allowing out-of-order execution of buffer operations while maintaining the ability to restore original packet order for reliable delivery. This enables parallel processing of multiple packets simultaneously.
Solution Approach 2:
The control section acts as an intermediary between the buffers and the packet delivery mechanism. It manages the sequence IDs and coordinates the reading/writing operations across multiple buffers, enabling out-of-order processing while ensuring that packets are ultimately delivered in the correct sequence to maintain reliability.
3Adaptability or versatility
If conventional bus bridges use FIFO buffers, then ease of manufacture is improved, but adaptability to virtual channel functions and packet overtaking control is limited
Solution Approach 1:
The patent implements dynamic buffer management where the control section can selectively read from and write to different buffers based on virtual channel requirements and packet priority. The buffer access mechanism is dynamic rather than static FIFO, allowing packet overtaking control where higher priority packets can be processed before lower priority ones, enabling virtual channel functions while maintaining manageable complexity through centralized control.
Data Source
AI summary
The present invention is a data transfer device, which comprises an input/output reception buffer, an input/output transmission buffer, a write data buffer, a read data buffer, a control information table, a write data storing process section, a write data transmission section, a read data buffer storing process section, an input/output transmission buffer storing process section and a control section that executes an access control for controlling the access to the memory by the write data transmission section and the read data buffer storing process section based on a control information table; thereby, a configuration optimum for both protocols of the memory bus and the input/output bus is obtained and the out-of-order execution is also achievable.