On-Chip Bus Bridge Transparent Encryption
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Solution Overview
Problem
Existing on-chip encryption and decryption techniques can slow down system performance due to resource-intensive computing requirements, making them vulnerable to tampering and access by malicious actors.
Innovation Solution
An on-chip high-performance bus bridge that transparently encrypts and decrypts data between the microprocessor and off-chip system memory, optimized for cache line size and bus protocol, using multiple cryptographic engines to minimize latency and throughput impact, with counter value and initial vector generators for secure operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encryption and decryption operations are performed using traditional computing resources, then code protection is achieved, but system performance and throughput are significantly slowed down
Solution Approach 1:
The patent replaces traditional software-based encryption/decryption mechanisms with dedicated hardware cryptographic engines integrated into the bus bridge. This hardware implementation performs encryption/decryption operations in parallel with data transfer, eliminating the sequential processing bottleneck and preventing performance degradation of the operating system and application programs.
Solution Approach 2:
The bus bridge acts as an intermediary component between the microprocessor and external memory, performing transparent encryption and decryption of data in transit. This mediator approach allows encryption/decryption to occur automatically during data transfer without requiring intervention from the processor or operating system, thus maintaining system performance while providing code protection.
2Reliability
If encryption operations are performed on every data transaction, then security is improved, but latency and processing time increase
Solution Approach 1:
The cryptographic engines are integrated into the data path of the bus bridge, allowing encryption and decryption to occur continuously during data transfer operations. The hardware engines process data in parallel with the transfer operation itself, eliminating sequential delays and maintaining continuous system operation without latency penalties.
Solution Approach 2:
The bus bridge is pre-configured with cryptographic engines and security parameters before data transactions occur. Encryption keys and algorithm configurations are established in advance, allowing immediate encryption/decryption of data as it passes through the bridge without requiring setup or processing delays during actual data transfer operations.
Data Source
AI summary
The disclosure is generally directed to a method and apparatus for encrypting and decrypting data on an integrated circuit. In various implementations, the apparatus includes an on-chip high performance bus bridge that transparently encrypts and decrypts data between the embedded microprocessor(s) and off-chip system memory. In some implementations, the apparatus is optimized to the transactions generated by the processor's cache controller (e.g., optimized for cache line size) and optimized to the bus protocol being used. This provides code protection with minimal effect on system performance latency and throughput. The implementation of multiple cryptographic engines allows for encryption of a complete cache line while incurring only a single latency for the first cipher rounds to be completed.