Bus Bridge Flush Control Circuit for Data Consistency

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Solution Overview

Problem

Data inconsistency issues arise in computer systems with bus bridges due to data buffering, leading to performance degradation when synchronization events occur and data remains posted in the bridge.

Innovation Solution

A flush request control circuit is implemented within the bridge to detect and record the flushing of buffers, generating a flush acknowledge signal once all buffers are cleared, allowing the system to continue processing transactions without interruption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data buffering is utilized in the bridge to enhance performance through packetizing and pre-fetching, then system performance is improved, but data consistency deteriorates when synchronization events occur and data remains posted in the bridge

Engineering Contradiction:
Improvesystem performanceVSAvoiddata consistency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The bridge performs preliminary flushing of buffers before synchronization events occur. The flush request control circuit proactively manages buffer contents by initiating flush operations to ensure data is transferred from the bridge to the memory bus before synchronization events, preventing data inconsistency while maintaining performance benefits of buffering

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The flush request control circuit implements feedback mechanisms by monitoring buffer status and generating flush acknowledge signals. When buffers are flushed, the circuit receives feedback through idle signals from buffers and generates corresponding flush acknowledge signals to the master device, ensuring data consistency is restored after buffering operations

Inventive Principle:
Principle #23Feedback

2Productivity

If data remains posted in the bridge during synchronization events, then buffering performance is maintained, but data inconsistency occurs

Engineering Contradiction:
Improvebuffering performanceVSAvoiddata consistency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The bridge dynamically adjusts its buffering behavior based on synchronization events. The flush request control circuit monitors system state and dynamically switches between normal buffering operation and flush mode when synchronization events occur, allowing the system to adapt buffer management strategies to maintain both performance and consistency

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention extracts and separates the data consistency management function from the general buffering function. By implementing a dedicated flush request control circuit that independently manages buffer flushing operations, the system can maintain buffering performance while separately addressing data consistency requirements through targeted flush operations

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If external master devices retry transactions when data inconsistency is detected, then data consistency is restored, but system performance deteriorates due to transaction retries

Engineering Contradiction:
Improvedata consistencyVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The bridge performs preliminary flush operations before synchronization events to prevent data inconsistency from occurring in the first place. By proactively flushing buffers before synchronization events, the system eliminates the need for subsequent transaction retries, maintaining both consistency and performance

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The flush request control circuit acts as an intermediary between the master device and the buffers. It receives flush requests from master devices, coordinates buffer flushing operations, and generates flush acknowledge signals, thereby mediating the data consistency management process and eliminating the need for master devices to retry transactions

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS7822906B2Data flush methods
Publication Date: 2010.10.26 VIA TECH INC
  • US7822906B2 patent drawing
  • US7822906B2 patent drawing
  • US7822906B2 patent drawing

AI summary

A bridge capable of preventing data inconsistency without degrading system performance is provided, in which a buffering unit comprises a plurality of buffers, a first master device outputs a flush request to flush the buffering unit, and a flush request control circuit records the flushed buffer(s) in the buffering unit when receiving the flush request and outputs a flush acknowledge signal to indicate to the first master device that the buffering unit has been flushed when all the plurality of buffers have been flushed once after the flush request has been received.