Bus Bridge Transaction Ordering for SoC Protocol Conversion

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Solution Overview

Problem

In complex Systems on Chips (SoCs), maintaining the order of transactions through a bus fabric is crucial for proper functioning, as existing technologies fail to ensure that read and write transactions are processed in the correct order, especially when transitioning between different bus protocols.

Innovation Solution

The implementation of control logic within a bridge that enforces the order of transactions by using separate connection paths for read and write transactions on the second bus, with a FIFO queue for write transactions and arbitration logic to select among them, while preventing read transactions from passing until all corresponding write transactions are completed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If separate connection paths are used for read and write transactions on the second bus, then transaction processing efficiency is improved, but transaction ordering is violated

Engineering Contradiction:
Improvetransaction processing efficiencyVSAvoidtransaction ordering
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A control logic unit acts as an intermediary between the first bus and the second bus, monitoring write transaction states and regulating read transaction forwarding to maintain proper ordering while allowing parallel processing paths

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The control logic continuously monitors the state of write transactions and uses this feedback information to dynamically control the forwarding of read transactions, ensuring that read transactions do not pass incomplete write transactions from the same source

Inventive Principle:
Principle #23Feedback

2Loss of time

If read transactions are allowed to pass write transactions, then latency is reduced, but data integrity is compromised

Engineering Contradiction:
Improvetransaction latencyVSAvoiddata integrity
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The forwarding control for read transactions is made dynamic rather than static, allowing read transactions to be forwarded when write transactions are complete but blocking them when writes are in progress, optimizing latency while maintaining integrity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The control logic serves as an intermediary that mediates between the desire to reduce latency by forwarding reads quickly and the need to maintain data integrity by ensuring proper ordering with respect to writes

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10324865B2Maintaining ordering requirements while converting protocols in a communications fabric
Publication Date: 2019.06.18 APPLE INC
  • US10324865B2 patent drawing
  • US10324865B2 patent drawing
  • US10324865B2 patent drawing

AI summary

Systems and methods for maintaining an order of read and write transactions for each source through a bridge in a bus fabric are disclosed. The bridge provides a connection from a first bus to a second bus within the bus fabric. The first bus has a single path for read and write transactions and the second bus has separate paths for read and write transactions. The bridge allows writes to pass reads for a given source, but prevents reads from passing writes. The bridge forwards a write transaction out of the bridge when the write transaction is available for forwarding. The bridge forwards a read transaction from a given source out of the bridge when there are no outstanding write transactions for the given source that are older than the read transaction. The bridge prevents forwarding the read transaction from the given source out of the bridge when there are outstanding write transactions that are older than the read transaction for the given source.