Bus Buffer Circuit With Output-State Check for Transition Accuracy
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Solution Overview
Problem
Conventional bus buffer circuits face the risk of temporarily outputting a potential different from the actual bus signal during output state transitions, leading to erroneous outputs due to internal signal states not matching the actual bus input signals.
Innovation Solution
A bus buffer circuit design that includes an input buffer, voltage conversion circuit, output retaining circuit, determinator, and three-state output buffer, which retains voltage-converted signals at the same potential level when the output enable signal is disabled, preventing erroneous outputs by maintaining a high impedance state during potential level equality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the internal circuit state is fixed to retain the inversion relationship in potential between the ordinary output and the inversion output, then current consumption during operation is reduced, but there is a risk that a potential different from the actual bus signal would be temporarily output during output state transition
Solution Approach 1:
The determinator circuit checks whether the internal circuit state matches the actual bus input signal before enabling the output buffer. This preliminary verification prevents erroneous output transitions by ensuring the internal state is synchronized with the actual bus signal before allowing output changes, thus maintaining reliability while keeping the circuit in a low-power fixed state during idle periods
Solution Approach 2:
The determinator circuit continuously monitors the relationship between the internal circuit state and the actual bus input signal, providing feedback control for the output enable signal. This feedback mechanism ensures that the output buffer is only enabled when the internal state accurately reflects the bus signal, preventing temporary erroneous outputs while maintaining the energy-efficient fixed state configuration
Data Source
AI summary
According to one embodiment, a bus buffer circuit includes an input buffer circuit that receives an input signal, and outputs a non-inversion input signal and an inversion input signal, a voltage conversion circuit that operates by a second power supply, performs voltage conversion on the non-inversion input signal and the inversion input signal input thereto, and outputs the signals as a voltage-converted non-inversion output signal and a voltage-converted inversion output signal, an output retaining circuit that retains the voltage-converted non-inversion output signal and the voltage-converted inversion output signal at a same potential level when an output enable signal is in a disable state, a determinator that determines whether these signals are at a same potential level, a three-state output buffer circuit that outputs the voltage-converted non-inversion output signal or the voltage-converted inversion output signal from an output terminal, and an output controller that sets the three-state output buffer circuit in an output disable state, when the voltage-converted non-inversion output signal and the voltage-converted inversion output signal are at a same potential level, on a basis of an outcome of the determinator. Therefore, it is possible to prevent a potential different from the actual bus signal from being temporarily output during an output state transition, in a case where the state is fixed to reduce the power consumption.