Bus Circuit Suppression for Oscillation Masking
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Solution Overview
Problem
Prolonged oscillations in bus voltage due to improper termination or topology lead to error-prone data transmission, especially with increased transmission rates, as existing solutions like masking bus oscillations are not effective in preventing erroneous activations.
Innovation Solution
A circuit with an ascertainment circuit that identifies a time window around the bit boundary where state transitions are most probable, activating a suppression circuit only within this window to mask short-term interferences and prevent erroneous activations, thereby enhancing communication robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the suppression circuit is activated continuously to mask bus oscillations, then the robustness of data transmission is improved, but erroneous activations occur outside the bit boundary time window causing unnecessary resistance changes
Solution Approach 1:
The patent divides the time domain into specific segments: a bit boundary time window where state transitions are expected and suppression is beneficial, and periods outside this window where suppression should not be active. The ascertainment circuit identifies the bit boundary time window based on transmission rate and bit time, and the suppression circuit is controlled to activate only within this segmented time period, preventing erroneous activations while maintaining transmission robustness.
2Reliability
If the suppression circuit is activated to reduce bus voltage oscillations, then communication robustness is increased, but the bit time is reduced due to increased transmission rates making detection more difficult
Solution Approach 1:
The patent calculates and prepares the bit boundary time window in advance based on the transmission rate and bit time parameters before actual data transmission occurs. This preliminary determination of the activation window allows the suppression circuit to be precisely controlled during high-speed transmission without adding detection complexity, as the time window parameters are pre-computed and ready for use.
Data Source
AI summary
A circuit for a bus system is provided. The circuit includes: an ascertainment circuit, which is configured to ascertain a first state in which an absolute difference of a voltage between two bus-side terminals is above a threshold value, to ascertain a second state in which the absolute value of the voltage between the two bus-side terminals is below the threshold value, to ascertain a bit boundary as a function of a number of state transitions between the first and second state, and to ascertain at least one time window, the start of which is situated before the bit boundary and the end of which is situated after the bit boundary; and a suppression circuit, which is configured to be activated when a state transition from the first state into the second state occurs within the ascertained time window.