Source Synchronous Bus Clock Encoding for Power Reduction
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Solution Overview
Problem
Source synchronous bus systems face high power consumption and electrical noise due to excessive clock and data valid signal transitions, leading to inefficiencies and synchronization issues.
Innovation Solution
The method involves encoding the clock signal with the data valid signal to reduce transitions, either by sending clock pulses only during valid data periods, using an internally generated clock, or by comparing data packets to minimize clock transitions, thereby reducing power consumption and noise generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock and data valid signals are continuously transmitted in source synchronous bus systems, then data transfer reliability is maintained, but power consumption increases and electrical noise is generated
Solution Approach 1:
The patent applies periodic action by transitioning from continuous clock signal transmission to periodic clock signal transmission. The clock signal is now transmitted only during valid data transfer periods and suspended during idle periods, creating a periodic rather than continuous operation mode. This reduces power consumption and electrical noise while maintaining data transfer reliability through proper timing synchronization at the receiver端.
2Reliability
If clock signal transitions are increased to mark each data valid period, then data synchronization is improved, but power consumption and noise increase
Solution Approach 1:
The patent extracts the data valid information from the continuous clock signal transitions and represents it more efficiently. Instead of using clock transitions for every data valid period, the system uses selective clock signal transmission only when data is valid, extracting the essential timing information while eliminating excessive transitions that generate noise.
3Manufacturing precision
If separate data valid signal is transmitted to mark valid data periods, then data timing accuracy is improved, but signal complexity and power consumption increase
Solution Approach 1:
The patent merges the data valid signaling function into the clock signal transmission itself. Instead of having separate clock and data valid signals, the clock signal's presence or absence indicates whether data is valid. This combining of functions reduces signal complexity and power consumption while maintaining timing accuracy through the clock signal's inherent timing properties.
Data Source
AI summary
Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, only the start and end of valid data packets are marked by clock signal transitions, or only a number of clock pulses that corresponds to number of data words is sent, or only a number transitions on clock signals are sent. The clock signal transitions may comprise either clock pulses or exclusively rising edge or falling edge transitions of the clock signal.