Bus Clock Line Handover for Power Management ICs
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Solution Overview
Problem
In power management systems with multiple PMICs on a single bus, the increased bus length and need for handover between PMICs lead to potential contention and misinterpretation of residual charges on the clock line, risking bus crashes and synchronization loss.
Innovation Solution
Implementing a bus clock line handover system where the original master continues to drive the clock line to a predetermined value after arbitration, allowing the incoming master to begin driving it simultaneously, ensuring continuous clock signal presence and reducing contention, with both masters driving the clock line to the same value during the transition to prevent misinterpretation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the original master releases the clock line immediately after arbitration loss, then the incoming master can quickly take control, but the clock line may float and cause slave devices to misinterpret residual charges as clock pulses
Solution Approach 1:
The original master device continues to drive the clock line to a known state (e.g., logical low) for a predetermined time period after arbitration loss, before releasing control. This preliminary action ensures the clock line is properly initialized and prevents floating states that could be misinterpreted by slave devices, while still allowing timely handover to the incoming master.
2Speed
If the incoming master drives the clock line immediately after winning arbitration, then control is transferred quickly, but contention may occur with the original master still driving the clock line
Solution Approach 1:
The incoming master device waits for a predetermined time period after winning arbitration before driving the clock line. This delay allows the original master to finish its predetermined drive period and release control, eliminating the risk of simultaneous driving and contention while maintaining efficient handover timing.
3Adaptability or versatility
If multiple PMICs are placed on a single power management bus to manage power supply, then power management capability is improved, but the bus length increases leading to potential contention and synchronization issues
Solution Approach 1:
The arbitration mechanism with predetermined delay periods ensures that when multiple PMICs share a long bus, only one master drives the clock line at any given time. The original master continues driving for a predetermined time after arbitration loss, and the incoming master waits for a predetermined time before taking control, preventing contention even over extended bus lengths with multiple devices.
Data Source
AI summary
Systems and methods for bus clock line handover are disclosed. In one aspect, a clock line in a bus is driven continuously during bus handover without having contentious or contradictory drive signals being provided. After arbitration, an original bus master will drive the clock line to a predetermined value until detecting a state change on a data line. An incoming bus master will begin driving the clock line to the predetermined value and then drive a state change on the data line. This state change is the state change detected by the original bus master that causes the original bus master to stop driving the clock line.